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authorRalf Baechle <ralf@linux-mips.org>2007-04-26 15:46:24 +0100
committerRalf Baechle <ralf@linux-mips.org>2007-04-27 16:20:23 +0100
commit78709b9df35346965b214e0e548412748d147776 (patch)
treeb2121c099b1a99901aed86921cce59e1f40d3bea /include/asm-mips
parent2127435e57a15f1fea8d6969e264eeb05b28ba4b (diff)
downloadop-kernel-dev-78709b9df35346965b214e0e548412748d147776.zip
op-kernel-dev-78709b9df35346965b214e0e548412748d147776.tar.gz
[MIPS] IP22: Get rid of volatile in IP22 core code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/sgi/hpc3.h2
-rw-r--r--include/asm-mips/sgi/ip22.h2
-rw-r--r--include/asm-mips/sgi/mc.h2
3 files changed, 3 insertions, 3 deletions
diff --git a/include/asm-mips/sgi/hpc3.h b/include/asm-mips/sgi/hpc3.h
index fcec52b..c4729f5 100644
--- a/include/asm-mips/sgi/hpc3.h
+++ b/include/asm-mips/sgi/hpc3.h
@@ -206,7 +206,7 @@ struct hpc3_regs {
#define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */
#define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */
- volatile u32 eeprom; /* EEPROM data reg. */
+ u32 eeprom; /* EEPROM data reg. */
#define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */
#define HPC3_EEPROM_CSEL 0x02 /* Chip select */
#define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */
diff --git a/include/asm-mips/sgi/ip22.h b/include/asm-mips/sgi/ip22.h
index 6592f3b..f4981c4 100644
--- a/include/asm-mips/sgi/ip22.h
+++ b/include/asm-mips/sgi/ip22.h
@@ -72,7 +72,7 @@
#define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE)
-extern unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg);
+extern unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg);
extern unsigned short ip22_nvram_read(int reg);
#endif
diff --git a/include/asm-mips/sgi/mc.h b/include/asm-mips/sgi/mc.h
index c52f783..1576c23 100644
--- a/include/asm-mips/sgi/mc.h
+++ b/include/asm-mips/sgi/mc.h
@@ -57,7 +57,7 @@ struct sgimc_regs {
volatile u32 divider; /* Divider reg for RPSS */
u32 _unused5;
- volatile u32 eeprom; /* EEPROM byte reg for r4k */
+ u32 eeprom; /* EEPROM byte reg for r4k */
#define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */
#define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */
#define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */
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