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| author | Len Brown <len.brown@intel.com> | 2005-09-08 01:45:47 -0400 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2005-09-08 01:45:47 -0400 |
| commit | 64e47488c913ac704d465a6af86a26786d1412a5 (patch) | |
| tree | d3b0148592963dcde26e4bb35ddfec8b1eaf8e23 /include/asm-mips/war.h | |
| parent | 4a35a46bf1cda4737c428380d1db5d15e2590d18 (diff) | |
| parent | caf39e87cc1182f7dae84eefc43ca14d54c78ef9 (diff) | |
| download | op-kernel-dev-64e47488c913ac704d465a6af86a26786d1412a5.zip op-kernel-dev-64e47488c913ac704d465a6af86a26786d1412a5.tar.gz | |
Merge linux-2.6 with linux-acpi-2.6
Diffstat (limited to 'include/asm-mips/war.h')
| -rw-r--r-- | include/asm-mips/war.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index c4a7041..04ee53b 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -113,7 +113,7 @@ */ #define BCM1250_M3_WAR 1 -/* +/* * This is a DUART workaround related to glitches around register accesses */ #define SIBYTE_1956_WAR 1 @@ -122,7 +122,7 @@ /* * Fill buffers not flushed on CACHE instructions - * + * * Hit_Invalidate_I cacheops invalidate an icache line but the refill * for that line can get stale data from the fill buffer instead of * accessing memory if the previous icache miss was also to that line. |
