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authorDavid Woodhouse <dwmw2@infradead.org>2007-10-13 14:43:54 +0100
committerDavid Woodhouse <dwmw2@infradead.org>2007-10-13 14:43:54 +0100
commitb160292cc216a50fd0cd386b0bda2cd48352c73b (patch)
treeef07cf98f91353ee4c9ec1e1ca7a2a5d9d4b538a /include/asm-mips/smtc.h
parentb37bde147890c8fea8369a5a4e230dabdea4ebfb (diff)
parentbbf25010f1a6b761914430f5fca081ec8c7accd1 (diff)
downloadop-kernel-dev-b160292cc216a50fd0cd386b0bda2cd48352c73b.zip
op-kernel-dev-b160292cc216a50fd0cd386b0bda2cd48352c73b.tar.gz
Merge Linux 2.6.23
Diffstat (limited to 'include/asm-mips/smtc.h')
-rw-r--r--include/asm-mips/smtc.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h
index 44dfa4a..ff3e893 100644
--- a/include/asm-mips/smtc.h
+++ b/include/asm-mips/smtc.h
@@ -55,4 +55,14 @@ extern void smtc_boot_secondary(int cpu, struct task_struct *t);
#define PARKED_INDEX ((unsigned int)0x80000000)
+/*
+ * Define low-level interrupt mask for IPIs, if necessary.
+ * By default, use SW interrupt 1, which requires no external
+ * hardware support, but which works only for single-core
+ * MIPS MT systems.
+ */
+#ifndef MIPS_CPU_IPI_IRQ
+#define MIPS_CPU_IPI_IRQ 1
+#endif
+
#endif /* _ASM_SMTC_MT_H */
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