diff options
| author | Sergei Shtylyov <sshtylyov@ru.mvista.com> | 2008-04-28 19:54:38 +0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-04-28 17:14:33 +0100 |
| commit | fcbd3b4b92efe29b59df16b910138cf43683be88 (patch) | |
| tree | 2aadd1e40849ea39e08fe41ee8772f38f27e6872 /include/asm-mips/mach-db1x00/db1200.h | |
| parent | df2700519c84ee8ee1e5ea165725c651f6d4d1a4 (diff) | |
| download | op-kernel-dev-fcbd3b4b92efe29b59df16b910138cf43683be88.zip op-kernel-dev-fcbd3b4b92efe29b59df16b910138cf43683be88.tar.gz | |
[MIPS] Pb1200/DBAu1200: move platform code to its proper place
Since both the IDE interface and SMC 91C111 Ethernet chip are on-board
devices, not SOC devices, move the platform device registration form the
common to the board specific code.
While at it, remove semicolon (which didn't break compilation only by
chance) from the AU1XXX_ATA_DDMA_REQ macro and do some renaming:
- change 'au1200_ide0_' variable name prefix to the mere 'ide_';
- change 'smc91x_' variable name prefix to 'smc91c111_' since that's the
name of the chip used on the boards;
- drop 'AU1XXX_' prefix from the names of macros describing IDE and Ethernet
on-board devices;
- change 'SMC91111_' to 'SMC91C111_', change 'IRQ' to 'INT' in the names of
the macros describing the Ethernet chip for consistency with the IDE
macros;
- change 'ATA_' to 'IDE_' and 'OFFSET' to 'SHIFT' (since this value is
indeed a shift count) in the names of the macros describing the IDE
interface.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mach-db1x00/db1200.h')
| -rw-r--r-- | include/asm-mips/mach-db1x00/db1200.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h index d2e28e6..eedd048 100644 --- a/include/asm-mips/mach-db1x00/db1200.h +++ b/include/asm-mips/mach-db1x00/db1200.h @@ -169,15 +169,15 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #define BCSR_INT_SD0INSERT 0x1000 #define BCSR_INT_SD0EJECT 0x2000 -#define AU1XXX_SMC91111_PHYS_ADDR (0x19000300) -#define AU1XXX_SMC91111_IRQ DB1200_ETH_INT - -#define AU1XXX_ATA_PHYS_ADDR (0x18800000) -#define AU1XXX_ATA_REG_OFFSET (5) -#define AU1XXX_ATA_PHYS_LEN (16 << AU1XXX_ATA_REG_OFFSET) -#define AU1XXX_ATA_INT DB1200_IDE_INT -#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1; -#define AU1XXX_ATA_RQSIZE 128 +#define SMC91C111_PHYS_ADDR 0x19000300 +#define SMC91C111_INT DB1200_ETH_INT + +#define IDE_PHYS_ADDR 0x18800000 +#define IDE_REG_SHIFT 5 +#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT) +#define IDE_INT DB1200_IDE_INT +#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 +#define IDE_RQSIZE 128 #define NAND_PHYS_ADDR 0x20000000 |
