Linux-2.6.12-rc2v2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!

4 files changed, 814 insertions, 0 deletions

diff --git a/include/asm-mips/ddb5xxx/ddb5074.h b/include/asm-mips/ddb5xxx/ddb5074.h
new file mode 100644
index 0000000..58d8830
--- /dev/null
+++ b/include/asm-mips/ddb5xxx/ddb5074.h
@@ -0,0 +1,38 @@
+/*
+ *  include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions
+ *
+ *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+ *                     Sony Software Development Center Europe (SDCE), Brussels
+ */
+
+#ifndef _ASM_DDB5XXX_DDB5074_H
+#define _ASM_DDB5XXX_DDB5074_H
+
+#include <asm/nile4.h>
+
+#define DDB_SDRAM_SIZE      0x04000000      /* 64MB */
+
+#define DDB_PCI_IO_BASE     0x06000000
+#define DDB_PCI_IO_SIZE     0x02000000      /* 32 MB */
+
+#define DDB_PCI_MEM_BASE    0x08000000
+#define DDB_PCI_MEM_SIZE    0x08000000  /* 128 MB */
+
+#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
+#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
+
+#define NILE4_PCI_IO_BASE   0xa6000000
+#define NILE4_PCI_MEM_BASE  0xa8000000
+#define NILE4_PCI_CFG_BASE  NILE4_PCI_MEM_BASE
+#define DDB_PCI_IACK_BASE NILE4_PCI_IO_BASE
+
+#define NILE4_IRQ_BASE NUM_I8259_INTERRUPTS
+#define CPU_IRQ_BASE (NUM_NILE4_INTERRUPTS + NILE4_IRQ_BASE)
+#define CPU_NILE4_CASCADE 2
+
+extern void ddb5074_led_hex(int hex);
+extern void ddb5074_led_d2(int on);
+extern void ddb5074_led_d3(int on);
+
+extern void nile4_irq_setup(u32 base);
+#endif
diff --git a/include/asm-mips/ddb5xxx/ddb5476.h b/include/asm-mips/ddb5xxx/ddb5476.h
new file mode 100644
index 0000000..4c23390
--- /dev/null
+++ b/include/asm-mips/ddb5xxx/ddb5476.h
@@ -0,0 +1,157 @@
+/*
+ * header file specific for ddb5476
+ *
+ * Copyright (C) 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+/*
+ *  Memory map (physical address)
+ *
+ *  Note most of the following address must be properly aligned by the
+ *  corresponding size.  For example, if PCI_IO_SIZE is 16MB, then
+ *  PCI_IO_BASE must be aligned along 16MB boundary.
+ */
+#define DDB_SDRAM_BASE		0x00000000
+#define DDB_SDRAM_SIZE		0x04000000      /* 64MB */
+
+#define	DDB_DCS3_BASE		0x04000000	/* flash 1 */
+#define	DDB_DCS3_SIZE		0x01000000	/* 16MB */
+
+#define	DDB_DCS2_BASE		0x05000000	/* flash 2 */
+#define	DDB_DCS2_SIZE		0x01000000	/* 16MB */
+
+#define DDB_PCI_IO_BASE		0x06000000
+#define DDB_PCI_IO_SIZE		0x02000000      /* 32 MB */
+
+#define	DDB_PCI_MEM_BASE	0x08000000
+#define	DDB_PCI_MEM_SIZE	0x08000000	/* 128 MB */
+
+#define	DDB_DCS5_BASE		0x13000000	/* DDB status regs */
+#define	DDB_DCS5_SIZE		0x00200000	/* 2MB, 8-bit */
+
+#define	DDB_DCS4_BASE		0x14000000	/* DDB control regs */
+#define	DDB_DCS4_SIZE		0x00200000	/* 2MB, 8-bit */
+
+#define DDB_INTCS_BASE		0x1fa00000      /* VRC5476 control regs */
+#define DDB_INTCS_SIZE		0x00200000      /* 2MB */
+
+#define DDB_BOOTCS_BASE         0x1fc00000      /* Boot ROM / EPROM /Flash */
+#define DDB_BOOTCS_SIZE         0x00200000      /* 2 MB - doc says 4MB */
+
+
+/* aliases */
+#define	DDB_PCI_CONFIG_BASE	DDB_PCI_MEM_BASE
+#define	DDB_PCI_CONFIG_SIZE	DDB_PCI_MEM_SIZE
+
+/* PCI intr ack share PCIW0 with PCI IO */
+#define	DDB_PCI_IACK_BASE	DDB_PCI_IO_BASE
+
+/*
+ * Interrupt mapping
+ *
+ * We have three interrupt controllers:
+ *
+ *   . CPU itself - 8 sources
+ *   . i8259 - 16 sources
+ *   . vrc5476 - 16 sources
+ *
+ *  They connected as follows:
+ *    all vrc5476 interrupts are routed to cpu IP2 (by software setting)
+ *    all i2869 are routed to INTC in vrc5476 (by hardware connection)
+ *
+ *  All VRC5476 PCI interrupts are level-triggered (no ack needed).
+ *  All PCI irq but INTC are active low.
+ */
+
+/*
+ * irq number block assignment
+ */
+
+#define	NUM_CPU_IRQ		8
+#define	NUM_I8259_IRQ		16
+#define	NUM_VRC5476_IRQ		16
+
+#define	DDB_IRQ_BASE		0
+
+#define	I8259_IRQ_BASE		DDB_IRQ_BASE
+#define	VRC5476_IRQ_BASE	(I8259_IRQ_BASE + NUM_I8259_IRQ)
+#define	CPU_IRQ_BASE		(VRC5476_IRQ_BASE + NUM_VRC5476_IRQ)
+
+/*
+ * vrc5476 irq defs, see page 52-64 of Vrc5074 system controller manual
+ */
+
+#define VRC5476_IRQ_CPCE	0	/* cpu parity error */
+#define VRC5476_IRQ_CNTD	1	/* cpu no target */
+#define VRC5476_IRQ_MCE		2	/* memory check error */
+#define VRC5476_IRQ_DMA		3	/* DMA */
+#define VRC5476_IRQ_UART	4	/* vrc5476 builtin UART, not used */
+#define VRC5476_IRQ_WDOG	5	/* watchdog timer */
+#define VRC5476_IRQ_GPT		6	/* general purpose timer */
+#define VRC5476_IRQ_LBRT	7	/* local bus read timeout */
+#define VRC5476_IRQ_INTA	8	/* PCI INT #A */
+#define VRC5476_IRQ_INTB	9	/* PCI INT #B */
+#define VRC5476_IRQ_INTC	10	/* PCI INT #C */
+#define VRC5476_IRQ_INTD	11	/* PCI INT #D */
+#define VRC5476_IRQ_INTE	12	/* PCI INT #E */
+#define VRC5476_IRQ_RESERVED_13	13	/* reserved  */
+#define VRC5476_IRQ_PCIS	14	/* PCI SERR #  */
+#define VRC5476_IRQ_PCI		15	/* PCI internal error */
+
+/*
+ * i2859 irq assignment
+ */
+#define I8259_IRQ_RESERVED_0	0
+#define I8259_IRQ_KEYBOARD	1	/* M1543 default */
+#define I8259_IRQ_CASCADE	2
+#define I8259_IRQ_UART_B	3	/* M1543 default, may conflict with RTC according to schematic diagram  */
+#define I8259_IRQ_UART_A	4	/* M1543 default */
+#define I8259_IRQ_PARALLEL	5	/* M1543 default */
+#define I8259_IRQ_RESERVED_6	6
+#define I8259_IRQ_RESERVED_7	7
+#define I8259_IRQ_RTC		8	/* who set this? */
+#define I8259_IRQ_USB		9	/* ddb_setup */
+#define I8259_IRQ_PMU		10	/* ddb_setup */
+#define I8259_IRQ_RESERVED_11	11
+#define I8259_IRQ_RESERVED_12	12	/* m1543_irq_setup */
+#define I8259_IRQ_RESERVED_13	13
+#define I8259_IRQ_HDC1		14	/* default and ddb_setup */
+#define I8259_IRQ_HDC2		15	/* default */
+
+
+/*
+ * misc
+ */
+#define	VRC5476_I8259_CASCADE	VRC5476_IRQ_INTC
+#define	CPU_VRC5476_CASCADE	2
+
+#define is_i8259_irq(irq)       ((irq) < NUM_I8259_IRQ)
+#define nile4_to_irq(n)         ((n)+NUM_I8259_IRQ)
+#define irq_to_nile4(n)         ((n)-NUM_I8259_IRQ)
+
+/*
+ * low-level irq functions
+ */
+#ifndef __ASSEMBLY__
+extern void nile4_map_irq(int nile4_irq, int cpu_irq);
+extern void nile4_map_irq_all(int cpu_irq);
+extern void nile4_enable_irq(int nile4_irq);
+extern void nile4_disable_irq(int nile4_irq);
+extern void nile4_disable_irq_all(void);
+extern u16 nile4_get_irq_stat(int cpu_irq);
+extern void nile4_enable_irq_output(int cpu_irq);
+extern void nile4_disable_irq_output(int cpu_irq);
+extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
+extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
+extern void nile4_clear_irq(int nile4_irq);
+extern void nile4_clear_irq_mask(u32 mask);
+extern u8 nile4_i8259_iack(void);
+extern void nile4_dump_irq_status(void);        /* Debug */
+#endif /* !__ASSEMBLY__ */
diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h
new file mode 100644
index 0000000..ae3e2a3
--- /dev/null
+++ b/include/asm-mips/ddb5xxx/ddb5477.h
@@ -0,0 +1,346 @@
+/***********************************************************************
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * include/asm-mips/ddb5xxx/ddb5477.h
+ *     DDB 5477 specific definitions and macros.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ ***********************************************************************
+ */
+
+#ifndef __ASM_DDB5XXX_DDB5477_H
+#define __ASM_DDB5XXX_DDB5477_H
+
+#include <linux/config.h>
+
+/*
+ * This contains macros that are specific to DDB5477 or renamed from
+ * DDB5476.
+ */
+
+/*
+ * renamed PADRs
+ */
+#define	DDB_LCS0	DDB_DCS2
+#define	DDB_LCS1	DDB_DCS3
+#define	DDB_LCS2	DDB_DCS4
+#define	DDB_VRC5477	DDB_INTCS
+
+/*
+ * New CPU interface registers
+ */
+#define	DDB_INTCTRL0	0x0400	/* Interrupt Control 0 */
+#define	DDB_INTCTRL1	0x0404	/* Interrupt Control 1 */
+#define	DDB_INTCTRL2	0x0408	/* Interrupt Control 2 */
+#define	DDB_INTCTRL3	0x040c	/* Interrupt Control 3 */
+
+#define	DDB_INT0STAT	0x0420 	/* INT0 Status [R] */
+#define	DDB_INT1STAT	0x0428 	/* INT1 Status [R] */
+#define	DDB_INT2STAT	0x0430 	/* INT2 Status [R] */
+#define	DDB_INT3STAT	0x0438 	/* INT3 Status [R] */
+#define	DDB_INT4STAT	0x0440 	/* INT4 Status [R] */
+#define	DDB_NMISTAT	0x0450	/* NMI Status [R] */
+
+#define	DDB_INTCLR32	0x0468	/* Interrupt Clear */
+
+#define	DDB_INTPPES0	0x0470	/* PCI0 Interrupt Control */
+#define	DDB_INTPPES1	0x0478	/* PCI1 Interrupt Control */
+
+#undef  DDB_CPUSTAT		/* duplicate in Vrc-5477 */
+#define	DDB_CPUSTAT	0x0480	/* CPU Status [R] */
+#define	DDB_BUSCTRL	0x0488	/* Internal Bus Control */
+
+
+/*
+ * Timer registers
+ */
+#define	DDB_REFCTRL_L	DDB_T0CTRL
+#define	DDB_REFCTRL_H	(DDB_T0CTRL+4)
+#define	DDB_REFCNTR	DDB_T0CNTR
+#define	DDB_SPT0CTRL_L	DDB_T1CTRL
+#define	DDB_SPT0CTRL_H	(DDB_T1CTRL+4)
+#define	DDB_SPT1CTRL_L	DDB_T2CTRL
+#define	DDB_SPT1CTRL_H	(DDB_T2CTRL+4)
+#define DDB_SPT1CNTR	DDB_T1CTRL
+#define	DDB_WDTCTRL_L	DDB_T3CTRL
+#define	DDB_WDTCTRL_H	(DDB_T3CTRL+4)
+#define	DDB_WDTCNTR	DDB_T3CNTR
+
+/*
+ * DMA registers are moved.  We don't care about it for now. TODO.
+ */
+
+/*
+ * BARs for ext PCI (PCI0)
+ */
+#undef	DDB_BARC
+#undef	DDB_BARB
+
+#define DDB_BARC0	0x0210	/* PCI0 Control */
+#define DDB_BARM010	0x0218	/* PCI0 SDRAM bank01 */
+#define	DDB_BARM230	0x0220	/* PCI0 SDRAM bank23 */
+#define	DDB_BAR00	0x0240	/* PCI0 LDCS0 */
+#define	DDB_BAR10	0x0248	/* PCI0 LDCS1 */
+#define	DDB_BAR20	0x0250	/* PCI0 LDCS2 */
+#define	DDB_BAR30	0x0258	/* PCI0 LDCS3 */
+#define	DDB_BAR40	0x0260	/* PCI0 LDCS4 */
+#define	DDB_BAR50	0x0268	/* PCI0 LDCS5 */
+#define	DDB_BARB0	0x0280	/* PCI0 BOOT */
+#define	DDB_BARP00	0x0290	/* PCI0 for IOPCI Window0 */
+#define	DDB_BARP10	0x0298	/* PCI0 for IOPCI Window1 */
+
+/*
+ * BARs for IOPIC (PCI1)
+ */
+#define DDB_BARC1	0x0610	/* PCI1 Control */
+#define DDB_BARM011	0x0618	/* PCI1 SDRAM bank01 */
+#define	DDB_BARM231	0x0620	/* PCI1 SDRAM bank23 */
+#define	DDB_BAR01	0x0640	/* PCI1 LDCS0 */
+#define	DDB_BAR11	0x0648	/* PCI1 LDCS1 */
+#define	DDB_BAR21	0x0650	/* PCI1 LDCS2 */
+#define	DDB_BAR31	0x0658	/* PCI1 LDCS3 */
+#define	DDB_BAR41	0x0660	/* PCI1 LDCS4 */
+#define	DDB_BAR51	0x0668	/* PCI1 LDCS5 */
+#define	DDB_BARB1	0x0680	/* PCI1 BOOT */
+#define	DDB_BARP01	0x0690	/* PCI1 for ext PCI Window0 */
+#define	DDB_BARP11	0x0698	/* PCI1 for ext PCI Window1 */
+
+/*
+ * Other registers for ext PCI (PCI0)
+ */
+#define	DDB_PCIINIT00	0x02f0	/* PCI0 Initiator 0 */
+#define	DDB_PCIINIT10	0x02f8	/* PCI0 Initiator 1 */
+
+#define	DDB_PCISWP0	0x02b0	/* PCI0 Swap */
+#define	DDB_PCIERR0	0x02b8	/* PCI0 Error */
+
+#define	DDB_PCICTL0_L	0x02e0	/* PCI0 Control-L */
+#define	DDB_PCICTL0_H	0x02e4	/* PCI0 Control-H */
+#define	DDB_PCIARB0_L	0x02e8	/* PCI0 Arbitration-L */
+#define	DDB_PCIARB0_H	0x02ec	/* PCI0 Arbitration-H */
+
+/*
+ * Other registers for IOPCI (PCI1)
+ */
+#define DDB_IOPCIW0	0x00d0	/* PCI Address Window 0 [R/W] */
+#define DDB_IOPCIW1	0x00d8	/* PCI Address Window 1 [R/W] */
+
+#define	DDB_PCIINIT01	0x06f0	/* PCI1 Initiator 0 */
+#define	DDB_PCIINIT11	0x06f8	/* PCI1 Initiator 1 */
+
+#define	DDB_PCISWP1	0x06b0	/* PCI1 Swap */
+#define	DDB_PCIERR1	0x06b8	/* PCI1 Error */
+
+#define	DDB_PCICTL1_L	0x06e0	/* PCI1 Control-L */
+#define	DDB_PCICTL1_H	0x06e4	/* PCI1 Control-H */
+#define	DDB_PCIARB1_L	0x06e8	/* PCI1 Arbitration-L */
+#define	DDB_PCIARB1_H	0x06ec	/* PCI1 Arbitration-H */
+
+/*
+ * Local Bus
+ */
+#define DDB_LCST0	0x0110  /* LB Chip Select Timing 0 */
+#define DDB_LCST1	0x0118  /* LB Chip Select Timing 1 */
+#undef DDB_LCST2
+#define DDB_LCST2	0x0120  /* LB Chip Select Timing 2 */
+#undef DDB_LCST3
+#undef DDB_LCST4
+#undef DDB_LCST5
+#undef DDB_LCST6
+#undef DDB_LCST7
+#undef DDB_LCST8
+#define DDB_ERRADR	0x0150  /* Error Address Register */
+#define DDB_ERRCS       0x0160
+#define DDB_BTM		0x0170  /* Boot Time Mode value */
+
+/*
+ * MISC registers
+ */
+#define DDB_GIUFUNSEL	0x4040  /* select dual-func pins */
+#define DDB_PIBMISC	0x0750	/* USB buffer enable / power saving */
+
+/*
+ *  Memory map (physical address)
+ *
+ *  Note most of the following address must be properly aligned by the
+ *  corresponding size.  For example, if PCI_IO_SIZE is 16MB, then
+ *  PCI_IO_BASE must be aligned along 16MB boundary.
+ */
+
+/* the actual ram size is detected at run-time */
+#define	DDB_SDRAM_BASE		0x00000000
+#define	DDB_MAX_SDRAM_SIZE	0x08000000	/* less than 128MB */
+
+#define	DDB_PCI0_MEM_BASE	0x08000000
+#define	DDB_PCI0_MEM_SIZE	0x08000000	/* 128 MB */
+
+#define	DDB_PCI1_MEM_BASE	0x10000000
+#define	DDB_PCI1_MEM_SIZE	0x08000000	/* 128 MB */
+
+#define	DDB_PCI0_CONFIG_BASE	0x18000000
+#define	DDB_PCI0_CONFIG_SIZE	0x01000000	/* 16 MB */
+
+#define	DDB_PCI1_CONFIG_BASE	0x19000000
+#define	DDB_PCI1_CONFIG_SIZE	0x01000000	/* 16 MB */
+
+#define	DDB_PCI_IO_BASE		0x1a000000	/* we concatenate two IOs */
+#define	DDB_PCI0_IO_BASE	0x1a000000
+#define	DDB_PCI0_IO_SIZE	0x01000000	/* 16 MB */
+#define	DDB_PCI1_IO_BASE	0x1b000000
+#define	DDB_PCI1_IO_SIZE	0x01000000	/* 16 MB */
+
+#define	DDB_LCS0_BASE		0x1c000000	/* flash memory */
+#define	DDB_LCS0_SIZE		0x01000000	/* 16 MB */
+
+#define	DDB_LCS1_BASE		0x1d000000	/* misc */
+#define	DDB_LCS1_SIZE		0x01000000	/* 16 MB */
+
+#define	DDB_LCS2_BASE		0x1e000000	/* Mezzanine */
+#define	DDB_LCS2_SIZE		0x01000000	/* 16 MB */
+
+#define	DDB_VRC5477_BASE	0x1fa00000	/* VRC5477 control regs */
+#define	DDB_VRC5477_SIZE	0x00200000	/* 2MB */
+
+#define	DDB_BOOTCS_BASE		0x1fc00000	/* Boot ROM / EPROM /Flash */
+#define	DDB_BOOTCS_SIZE		0x00200000	/* 2 MB - doc says 4MB */
+
+#define	DDB_LED			DDB_LCS1_BASE + 0x10000
+
+
+/*
+ * DDB5477 specific functions
+ */
+#ifndef __ASSEMBLY__
+extern void ddb5477_irq_setup(void);
+
+/* route irq to cpu int pin */
+extern void ll_vrc5477_irq_route(int vrc5477_irq, int ip);
+
+/* low-level routine for enabling vrc5477 irq, bypassing high-level */
+extern void ll_vrc5477_irq_enable(int vrc5477_irq);
+extern void ll_vrc5477_irq_disable(int vrc5477_irq);
+#endif /* !__ASSEMBLY__ */
+
+/* PCI intr ack share PCIW0 with PCI IO */
+#define	DDB_PCI_IACK_BASE	DDB_PCI_IO_BASE
+
+/*
+ * Interrupt mapping
+ *
+ * We have three interrupt controllers:
+ *
+ *   . CPU itself - 8 sources
+ *   . i8259 - 16 sources
+ *   . vrc5477 - 32 sources
+ *
+ *  They connected as follows:
+ *    all vrc5477 interrupts are routed to cpu IP2 (by software setting)
+ *    all i8359 are routed to INTC in vrc5477 (by hardware connection)
+ *
+ *  All VRC5477 PCI interrupts are level-triggered (no ack needed).
+ *  All PCI irq but INTC are active low.
+ */
+
+/* 
+ * irq number block assignment
+ */
+
+#define	NUM_CPU_IRQ		8
+#define	NUM_I8259_IRQ		16
+#define	NUM_VRC5477_IRQ		32
+
+#define	DDB_IRQ_BASE		0
+
+#define	I8259_IRQ_BASE		DDB_IRQ_BASE
+#define	VRC5477_IRQ_BASE	(I8259_IRQ_BASE + NUM_I8259_IRQ)
+#define	CPU_IRQ_BASE		(VRC5477_IRQ_BASE + NUM_VRC5477_IRQ)
+
+/*
+ * vrc5477 irq defs
+ */
+
+#define VRC5477_IRQ_CPCE	(0 + VRC5477_IRQ_BASE)	/* cpu parity error */
+#define VRC5477_IRQ_CNTD	(1 + VRC5477_IRQ_BASE)	/* cpu no target */
+#define VRC5477_IRQ_I2C		(2 + VRC5477_IRQ_BASE)	/* I2C */
+#define VRC5477_IRQ_DMA		(3 + VRC5477_IRQ_BASE)	/* DMA */
+#define VRC5477_IRQ_UART0	(4 + VRC5477_IRQ_BASE)
+#define VRC5477_IRQ_WDOG	(5 + VRC5477_IRQ_BASE)	/* watchdog timer */
+#define VRC5477_IRQ_SPT1	(6 + VRC5477_IRQ_BASE)    /* special purpose timer 1 */
+#define VRC5477_IRQ_LBRT	(7 + VRC5477_IRQ_BASE)	/* local bus read timeout */
+#define VRC5477_IRQ_INTA	(8 + VRC5477_IRQ_BASE)	/* PCI INT #A */
+#define VRC5477_IRQ_INTB	(9 + VRC5477_IRQ_BASE)	/* PCI INT #B */
+#define VRC5477_IRQ_INTC	(10 + VRC5477_IRQ_BASE)	/* PCI INT #C */
+#define VRC5477_IRQ_INTD	(11 + VRC5477_IRQ_BASE)	/* PCI INT #D */
+#define VRC5477_IRQ_INTE	(12 + VRC5477_IRQ_BASE)	/* PCI INT #E */
+#define VRC5477_IRQ_RESERVED_13	(13 + VRC5477_IRQ_BASE)	/* reserved  */
+#define VRC5477_IRQ_PCIS	(14 + VRC5477_IRQ_BASE)	/* PCI SERR #  */
+#define VRC5477_IRQ_PCI		(15 + VRC5477_IRQ_BASE)	/* PCI internal error */
+#define VRC5477_IRQ_IOPCI_INTA	(16 + VRC5477_IRQ_BASE)      /* USB-H */
+#define VRC5477_IRQ_IOPCI_INTB	(17 + VRC5477_IRQ_BASE)      /* USB-P */
+#define VRC5477_IRQ_IOPCI_INTC	(18 + VRC5477_IRQ_BASE)      /* AC97 */
+#define VRC5477_IRQ_IOPCI_INTD	(19 + VRC5477_IRQ_BASE)      /* Reserved */
+#define VRC5477_IRQ_UART1	(20 + VRC5477_IRQ_BASE)     
+#define VRC5477_IRQ_SPT0	(21 + VRC5477_IRQ_BASE)      /* special purpose timer 0 */
+#define VRC5477_IRQ_GPT0	(22 + VRC5477_IRQ_BASE)      /* general purpose timer 0 */
+#define VRC5477_IRQ_GPT1	(23 + VRC5477_IRQ_BASE)      /* general purpose timer 1 */
+#define VRC5477_IRQ_GPT2	(24 + VRC5477_IRQ_BASE)      /* general purpose timer 2 */
+#define VRC5477_IRQ_GPT3	(25 + VRC5477_IRQ_BASE)      /* general purpose timer 3 */
+#define VRC5477_IRQ_GPIO	(26 + VRC5477_IRQ_BASE)
+#define VRC5477_IRQ_SIO0	(27 + VRC5477_IRQ_BASE)
+#define VRC5477_IRQ_SIO1        (28 + VRC5477_IRQ_BASE)
+#define VRC5477_IRQ_RESERVED_29 (29 + VRC5477_IRQ_BASE)      /* reserved */
+#define VRC5477_IRQ_IOPCISERR	(30 + VRC5477_IRQ_BASE)      /* IO PCI SERR # */
+#define VRC5477_IRQ_IOPCI	(31 + VRC5477_IRQ_BASE)
+
+/*
+ * i2859 irq assignment
+ */
+#define I8259_IRQ_RESERVED_0	(0 + I8259_IRQ_BASE)	
+#define I8259_IRQ_KEYBOARD	(1 + I8259_IRQ_BASE)	/* M1543 default */
+#define I8259_IRQ_CASCADE	(2 + I8259_IRQ_BASE)
+#define I8259_IRQ_UART_B	(3 + I8259_IRQ_BASE)	/* M1543 default, may conflict with RTC according to schematic diagram  */
+#define I8259_IRQ_UART_A	(4 + I8259_IRQ_BASE)	/* M1543 default */
+#define I8259_IRQ_PARALLEL	(5 + I8259_IRQ_BASE)	/* M1543 default */
+#define I8259_IRQ_RESERVED_6	(6 + I8259_IRQ_BASE)
+#define I8259_IRQ_RESERVED_7	(7 + I8259_IRQ_BASE)
+#define I8259_IRQ_RTC		(8 + I8259_IRQ_BASE)	/* who set this? */
+#define I8259_IRQ_USB		(9 + I8259_IRQ_BASE)	/* ddb_setup */
+#define I8259_IRQ_PMU		(10 + I8259_IRQ_BASE)	/* ddb_setup */
+#define I8259_IRQ_RESERVED_11	(11 + I8259_IRQ_BASE)
+#define I8259_IRQ_RESERVED_12	(12 + I8259_IRQ_BASE)	/* m1543_irq_setup */
+#define I8259_IRQ_RESERVED_13	(13 + I8259_IRQ_BASE)
+#define I8259_IRQ_HDC1		(14 + I8259_IRQ_BASE)	/* default and ddb_setup */
+#define I8259_IRQ_HDC2		(15 + I8259_IRQ_BASE)	/* default */
+
+
+/*
+ * misc
+ */
+#define	VRC5477_I8259_CASCADE	(VRC5477_IRQ_INTC - VRC5477_IRQ_BASE)
+#define	CPU_VRC5477_CASCADE	2
+
+/*
+ * debug routines
+ */
+#ifndef __ASSEMBLY__
+#if defined(CONFIG_RUNTIME_DEBUG)
+extern void vrc5477_show_pdar_regs(void);
+extern void vrc5477_show_pci_regs(void);
+extern void vrc5477_show_bar_regs(void);
+extern void vrc5477_show_int_regs(void);
+extern void vrc5477_show_all_regs(void);
+#endif
+
+/*
+ * RAM size
+ */
+extern int board_ram_size;
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_DDB5XXX_DDB5477_H */
diff --git a/include/asm-mips/ddb5xxx/ddb5xxx.h b/include/asm-mips/ddb5xxx/ddb5xxx.h
new file mode 100644
index 0000000..873c03f
--- /dev/null
+++ b/include/asm-mips/ddb5xxx/ddb5xxx.h
@@ -0,0 +1,273 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+ *                    Sony Software Development Center Europe (SDCE), Brussels
+ *
+ * include/asm-mips/ddb5xxx/ddb5xxx.h
+ *     Common header for all NEC DDB 5xxx boards, including 5074, 5476, 5477.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __ASM_DDB5XXX_DDB5XXX_H
+#define __ASM_DDB5XXX_DDB5XXX_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+
+/*
+ *  This file is based on the following documentation:
+ *
+ *	NEC Vrc 5074 System Controller Data Sheet, June 1998
+ *
+ * [jsun] It is modified so that this file only contains the macros
+ * that are true for all DDB 5xxx boards.  The modification is based on
+ *
+ *	uPD31577(VRC5477) VR5432-SDRAM/PCI Bridge (Luke)
+ *	Preliminary Specification Decoment, Rev 1.1, 27 Dec, 2000
+ *
+ */
+
+
+#define DDB_BASE		0xbfa00000
+#define DDB_SIZE		0x00200000		/* 2 MB */
+
+
+/*
+ *  Physical Device Address Registers (PDARs)
+ */
+
+#define DDB_SDRAM0	0x0000	/* SDRAM Bank 0 [R/W] */
+#define DDB_SDRAM1	0x0008	/* SDRAM Bank 1 [R/W] */
+#define DDB_DCS2	0x0010	/* Device Chip-Select 2 [R/W] */
+#define DDB_DCS3	0x0018	/* Device Chip-Select 3 [R/W] */
+#define DDB_DCS4	0x0020	/* Device Chip-Select 4 [R/W] */
+#define DDB_DCS5	0x0028	/* Device Chip-Select 5 [R/W] */
+#define DDB_DCS6	0x0030	/* Device Chip-Select 6 [R/W] */
+#define DDB_DCS7	0x0038	/* Device Chip-Select 7 [R/W] */
+#define DDB_DCS8	0x0040	/* Device Chip-Select 8 [R/W] */
+#define DDB_PCIW0	0x0060	/* PCI Address Window 0 [R/W] */
+#define DDB_PCIW1	0x0068	/* PCI Address Window 1 [R/W] */
+#define DDB_INTCS	0x0070	/* Controller Internal Registers and Devices */
+				/* [R/W] */
+#define DDB_BOOTCS	0x0078	/* Boot ROM Chip-Select [R/W] */
+/* Vrc5477 has two more, IOPCIW0, IOPCIW1 */
+
+/*
+ *  CPU Interface Registers
+ */
+#define DDB_CPUSTAT	0x0080	/* CPU Status [R/W] */
+#define DDB_INTCTRL	0x0088	/* Interrupt Control [R/W] */
+#define DDB_INTSTAT0	0x0090	/* Interrupt Status 0 [R] */
+#define DDB_INTSTAT1	0x0098	/* Interrupt Status 1 and CPU Interrupt */
+				/* Enable [R/W] */
+#define DDB_INTCLR	0x00A0	/* Interrupt Clear [R/W] */
+#define DDB_INTPPES	0x00A8	/* PCI Interrupt Control [R/W] */
+
+
+/*
+ *  Memory-Interface Registers
+ */
+#define DDB_MEMCTRL	0x00C0	/* Memory Control */
+#define DDB_ACSTIME	0x00C8	/* Memory Access Timing [R/W] */
+#define DDB_CHKERR	0x00D0	/* Memory Check Error Status [R] */
+
+
+/*
+ *  PCI-Bus Registers
+ */
+#define DDB_PCICTRL	0x00E0	/* PCI Control [R/W] */
+#define DDB_PCIARB	0x00E8	/* PCI Arbiter [R/W] */
+#define DDB_PCIINIT0	0x00F0	/* PCI Master (Initiator) 0 [R/W] */
+#define DDB_PCIINIT1	0x00F8	/* PCI Master (Initiator) 1 [R/W] */
+#define DDB_PCIERR	0x00B8	/* PCI Error [R/W] */
+
+
+/*
+ *  Local-Bus Registers
+ */
+#define DDB_LCNFG	0x0100	/* Local Bus Configuration [R/W] */
+#define DDB_LCST2	0x0110	/* Local Bus Chip-Select Timing 2 [R/W] */
+#define DDB_LCST3	0x0118	/* Local Bus Chip-Select Timing 3 [R/W] */
+#define DDB_LCST4	0x0120	/* Local Bus Chip-Select Timing 4 [R/W] */
+#define DDB_LCST5	0x0128	/* Local Bus Chip-Select Timing 5 [R/W] */
+#define DDB_LCST6	0x0130	/* Local Bus Chip-Select Timing 6 [R/W] */
+#define DDB_LCST7	0x0138	/* Local Bus Chip-Select Timing 7 [R/W] */
+#define DDB_LCST8	0x0140	/* Local Bus Chip-Select Timing 8 [R/W] */
+#define DDB_DCSFN	0x0150	/* Device Chip-Select Muxing and Output */
+				/* Enables [R/W] */
+#define DDB_DCSIO	0x0158	/* Device Chip-Selects As I/O Bits [R/W] */
+#define DDB_BCST	0x0178	/* Local Boot Chip-Select Timing [R/W] */
+
+
+/*
+ *  DMA Registers
+ */
+#define DDB_DMACTRL0	0x0180	/* DMA Control 0 [R/W] */
+#define DDB_DMASRCA0	0x0188	/* DMA Source Address 0 [R/W] */
+#define DDB_DMADESA0	0x0190	/* DMA Destination Address 0 [R/W] */
+#define DDB_DMACTRL1	0x0198	/* DMA Control 1 [R/W] */
+#define DDB_DMASRCA1	0x01A0	/* DMA Source Address 1 [R/W] */
+#define DDB_DMADESA1	0x01A8	/* DMA Destination Address 1 [R/W] */
+
+
+/*
+ *  Timer Registers
+ */
+#define DDB_T0CTRL	0x01C0	/* SDRAM Refresh Control [R/W] */
+#define DDB_T0CNTR	0x01C8	/* SDRAM Refresh Counter [R/W] */
+#define DDB_T1CTRL	0x01D0	/* CPU-Bus Read Time-Out Control [R/W] */
+#define DDB_T1CNTR	0x01D8	/* CPU-Bus Read Time-Out Counter [R/W] */
+#define DDB_T2CTRL	0x01E0	/* General-Purpose Timer Control [R/W] */
+#define DDB_T2CNTR	0x01E8	/* General-Purpose Timer Counter [R/W] */
+#define DDB_T3CTRL	0x01F0	/* Watchdog Timer Control [R/W] */
+#define DDB_T3CNTR	0x01F8	/* Watchdog Timer Counter [R/W] */
+
+
+/*
+ *  PCI Configuration Space Registers
+ */
+#define DDB_PCI_BASE	0x0200
+
+#define DDB_VID		0x0200	/* PCI Vendor ID [R] */
+#define DDB_DID		0x0202	/* PCI Device ID [R] */
+#define DDB_PCICMD	0x0204	/* PCI Command [R/W] */
+#define DDB_PCISTS	0x0206	/* PCI Status [R/W] */
+#define DDB_REVID	0x0208	/* PCI Revision ID [R] */
+#define DDB_CLASS	0x0209	/* PCI Class Code [R] */
+#define DDB_CLSIZ	0x020C	/* PCI Cache Line Size [R/W] */
+#define DDB_MLTIM	0x020D	/* PCI Latency Timer [R/W] */
+#define DDB_HTYPE	0x020E	/* PCI Header Type [R] */
+#define DDB_BIST	0x020F	/* BIST [R] (unimplemented) */
+#define DDB_BARC	0x0210	/* PCI Base Address Register Control [R/W] */
+#define DDB_BAR0	0x0218	/* PCI Base Address Register 0 [R/W] */
+#define DDB_BAR1	0x0220	/* PCI Base Address Register 1 [R/W] */
+#define DDB_CIS		0x0228	/* PCI Cardbus CIS Pointer [R] */
+				/* (unimplemented) */
+#define DDB_SSVID	0x022C	/* PCI Sub-System Vendor ID [R/W] */
+#define DDB_SSID	0x022E	/* PCI Sub-System ID [R/W] */
+#define DDB_ROM		0x0230	/* Expansion ROM Base Address [R] */
+				/* (unimplemented) */
+#define DDB_INTLIN	0x023C	/* PCI Interrupt Line [R/W] */
+#define DDB_INTPIN	0x023D	/* PCI Interrupt Pin [R] */
+#define DDB_MINGNT	0x023E	/* PCI Min_Gnt [R] (unimplemented) */
+#define DDB_MAXLAT	0x023F	/* PCI Max_Lat [R] (unimplemented) */
+#define DDB_BAR2	0x0240	/* PCI Base Address Register 2 [R/W] */
+#define DDB_BAR3	0x0248	/* PCI Base Address Register 3 [R/W] */
+#define DDB_BAR4	0x0250	/* PCI Base Address Register 4 [R/W] */
+#define DDB_BAR5	0x0258	/* PCI Base Address Register 5 [R/W] */
+#define DDB_BAR6	0x0260	/* PCI Base Address Register 6 [R/W] */
+#define DDB_BAR7	0x0268	/* PCI Base Address Register 7 [R/W] */
+#define DDB_BAR8	0x0270	/* PCI Base Address Register 8 [R/W] */
+#define DDB_BARB	0x0278	/* PCI Base Address Register BOOT [R/W] */
+
+
+/*
+ *  Nile 4 Register Access
+ */
+
+static inline void ddb_sync(void)
+{
+/* The DDB5074 doesn't seem to like these accesses. They kill the board on
+ * interrupt load
+ */
+#ifndef CONFIG_DDB5074
+    volatile u32 *p = (volatile u32 *)0xbfc00000;
+    (void)(*p);
+#endif
+}
+
+static inline void ddb_out32(u32 offset, u32 val)
+{
+    *(volatile u32 *)(DDB_BASE+offset) = val;
+    ddb_sync();
+}
+
+static inline u32 ddb_in32(u32 offset)
+{
+    u32 val = *(volatile u32 *)(DDB_BASE+offset);
+    ddb_sync();
+    return val;
+}
+
+static inline void ddb_out16(u32 offset, u16 val)
+{
+    *(volatile u16 *)(DDB_BASE+offset) = val;
+    ddb_sync();
+}
+
+static inline u16 ddb_in16(u32 offset)
+{
+    u16 val = *(volatile u16 *)(DDB_BASE+offset);
+    ddb_sync();
+    return val;
+}
+
+static inline void ddb_out8(u32 offset, u8 val)
+{
+    *(volatile u8 *)(DDB_BASE+offset) = val;
+    ddb_sync();
+}
+
+static inline u8 ddb_in8(u32 offset)
+{
+    u8 val = *(volatile u8 *)(DDB_BASE+offset);
+    ddb_sync();
+    return val;
+}
+
+
+/*
+ *  Physical Device Address Registers
+ */
+
+extern u32
+ddb_calc_pdar(u32 phys, u32 size, int width, int on_memory_bus, int pci_visible);
+extern void
+ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width,
+	     int on_memory_bus, int pci_visible);
+
+/*
+ *  PCI Master Registers
+ */
+
+#define DDB_PCICMD_IACK		0	/* PCI Interrupt Acknowledge */
+#define DDB_PCICMD_IO		1	/* PCI I/O Space */
+#define DDB_PCICMD_MEM		3	/* PCI Memory Space */
+#define DDB_PCICMD_CFG		5	/* PCI Configuration Space */
+
+/*
+ * additional options for pci init reg (no shifting needed)
+ */
+#define DDB_PCI_CFGTYPE1     0x200   /* for pci init0/1 regs */
+#define DDB_PCI_ACCESS_32    0x10    /* for pci init0/1 regs */
+
+
+extern void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options);
+
+/*
+ * we need to reset pci bus when we start up and shutdown
+ */
+extern void ddb_pci_reset_bus(void);
+
+
+/*
+ * include the board dependent part
+ */
+#if defined(CONFIG_DDB5074)
+#include <asm/ddb5xxx/ddb5074.h>
+#elif defined(CONFIG_DDB5476)
+#include <asm/ddb5xxx/ddb5476.h>
+#elif defined(CONFIG_DDB5477)
+#include <asm/ddb5xxx/ddb5477.h>
+#else
+#error "Unknown DDB board!"
+#endif
+
+#endif /* __ASM_DDB5XXX_DDB5XXX_H */