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authorRalf Baechle <ralf@linux-mips.org>2006-07-06 13:04:01 +0100
committerRalf Baechle <ralf@linux-mips.org>2006-07-13 21:26:04 +0100
commitfc5d2d279ff820172a698706d33e733d4578bd6c (patch)
tree1b376605e1870af29a49272d85cb589d319e058b /include/asm-mips/cpu.h
parent879ba8c88a32f2bd3d3369837afdc148bd66bb04 (diff)
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op-kernel-dev-fc5d2d279ff820172a698706d33e733d4578bd6c.tar.gz
[MIPS] Use the proper technical term for naming some of the cache macros.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/cpu.h')
-rw-r--r--include/asm-mips/cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index dff2a0a..d38fdbf 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -242,7 +242,7 @@
#define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */
#define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */
#define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */
-#define MIPS_CPU_SUBSET_CACHES 0x00040000 /* P-cache subset enforced */
+#define MIPS_CPU_INCLUSIVE_CACHES 0x00040000 /* P-cache subset enforced */
#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */
#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */
#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */
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