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| author | Ralf Baechle <ralf@linux-mips.org> | 2006-04-05 09:45:45 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-04-19 04:14:28 +0200 |
| commit | 41c594ab65fc89573af296d192aa5235d09717ab (patch) | |
| tree | 562462512a320f386bdf49eabfbb26bb3ee761fa /include/asm-mips/cpu-info.h | |
| parent | 2600990e640e3bef29ed89d565864cf16ee83833 (diff) | |
| download | op-kernel-dev-41c594ab65fc89573af296d192aa5235d09717ab.zip op-kernel-dev-41c594ab65fc89573af296d192aa5235d09717ab.tar.gz | |
[MIPS] MT: Improved multithreading support.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/cpu-info.h')
| -rw-r--r-- | include/asm-mips/cpu-info.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h index 140be1c..6572ac7 100644 --- a/include/asm-mips/cpu-info.h +++ b/include/asm-mips/cpu-info.h @@ -73,6 +73,16 @@ struct cpuinfo_mips { struct cache_desc dcache; /* Primary D or combined I/D cache */ struct cache_desc scache; /* Secondary cache */ struct cache_desc tcache; /* Tertiary/split secondary cache */ +#if defined(CONFIG_MIPS_MT_SMTC) + /* + * In the MIPS MT "SMTC" model, each TC is considered + * to be a "CPU" for the purposes of scheduling, but + * exception resources, ASID spaces, etc, are common + * to all TCs within the same VPE. + */ + int vpe_id; /* Virtual Processor number */ + int tc_id; /* Thread Context number */ +#endif /* CONFIG_MIPS_MT */ void *data; /* Additional data */ } __attribute__((aligned(SMP_CACHE_BYTES))); |
