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| author | Jonathan Corbet <corbet@lwn.net> | 2008-07-14 15:29:34 -0600 |
|---|---|---|
| committer | Jonathan Corbet <corbet@lwn.net> | 2008-07-14 15:29:34 -0600 |
| commit | 2fceef397f9880b212a74c418290ce69e7ac00eb (patch) | |
| tree | d9cc09ab992825ef7fede4a688103503e3caf655 /include/asm-mips/cpu-info.h | |
| parent | feae1ef116ed381625d3731c5ae4f4ebcb3fa302 (diff) | |
| parent | bce7f793daec3e65ec5c5705d2457b81fe7b5725 (diff) | |
| download | op-kernel-dev-2fceef397f9880b212a74c418290ce69e7ac00eb.zip op-kernel-dev-2fceef397f9880b212a74c418290ce69e7ac00eb.tar.gz | |
Merge commit 'v2.6.26' into bkl-removal
Diffstat (limited to 'include/asm-mips/cpu-info.h')
| -rw-r--r-- | include/asm-mips/cpu-info.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h index 0c5a358..2de73db 100644 --- a/include/asm-mips/cpu-info.h +++ b/include/asm-mips/cpu-info.h @@ -56,7 +56,7 @@ struct cpuinfo_mips { struct cache_desc tcache; /* Tertiary/split secondary cache */ int srsets; /* Shadow register sets */ int core; /* physical core number */ -#if defined(CONFIG_MIPS_MT_SMTC) +#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) /* * In the MIPS MT "SMTC" model, each TC is considered * to be a "CPU" for the purposes of scheduling, but @@ -64,7 +64,7 @@ struct cpuinfo_mips { * to all TCs within the same VPE. */ int vpe_id; /* Virtual Processor number */ -#endif /* CONFIG_MIPS_MT */ +#endif #ifdef CONFIG_MIPS_MT_SMTC int tc_id; /* Thread Context number */ #endif |
