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| author | Ralf Baechle <ralf@linux-mips.org> | 2005-02-21 16:18:36 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 19:30:42 +0100 |
| commit | c4ed38a0c6e2e5c4906296758f816ee71373792f (patch) | |
| tree | 65ebab9ca61ea6d03109c53acd2989b626dce52a /include/asm-mips/cobalt/cobalt.h | |
| parent | 049b13c358f0187cf3c5003d5fb9848dbcb28bc3 (diff) | |
| download | op-kernel-dev-c4ed38a0c6e2e5c4906296758f816ee71373792f.zip op-kernel-dev-c4ed38a0c6e2e5c4906296758f816ee71373792f.tar.gz | |
Resurrect Cobalt support for 2.6.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/cobalt/cobalt.h')
| -rw-r--r-- | include/asm-mips/cobalt/cobalt.h | 52 |
1 files changed, 39 insertions, 13 deletions
diff --git a/include/asm-mips/cobalt/cobalt.h b/include/asm-mips/cobalt/cobalt.h index ca1fbc0..78e1df2 100644 --- a/include/asm-mips/cobalt/cobalt.h +++ b/include/asm-mips/cobalt/cobalt.h @@ -19,18 +19,23 @@ * 9 - PCI * 14 - IDE0 * 15 - IDE1 - * + */ +#define COBALT_QUBE_SLOT_IRQ 9 + +/* * CPU IRQs are 16 ... 23 */ -#define COBALT_TIMER_IRQ 18 -#define COBALT_SCC_IRQ 19 /* pre-production has 85C30 */ -#define COBALT_RAQ_SCSI_IRQ 19 -#define COBALT_ETH0_IRQ 19 -#define COBALT_ETH1_IRQ 20 -#define COBALT_SERIAL_IRQ 21 -#define COBALT_SCSI_IRQ 21 -#define COBALT_VIA_IRQ 22 /* Chained to VIA ISA bridge */ -#define COBALT_QUBE_SLOT_IRQ 23 +#define COBALT_CPU_IRQ 16 + +#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2) +#define COBALT_SCC_IRQ (COBALT_CPU_IRQ + 3) /* pre-production has 85C30 */ +#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3) +#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3) +#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4) +#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4) +#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5) +#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5) +#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */ /* * PCI configuration space manifest constants. These are wired into @@ -69,16 +74,21 @@ * Most of this really should go into a separate GT64111 header file. */ #define GT64111_IO_BASE 0x10000000UL +#define GT64111_IO_END 0x11ffffffUL +#define GT64111_MEM_BASE 0x12000000UL +#define GT64111_MEM_END 0x13ffffffUL #define GT64111_BASE 0x14000000UL -#define GALILEO_REG(ofs) (KSEG0 + GT64111_BASE + (unsigned long)(ofs)) +#define GALILEO_REG(ofs) CKSEG1ADDR(GT64111_BASE + (unsigned long)(ofs)) #define GALILEO_INL(port) (*(volatile unsigned int *) GALILEO_REG(port)) #define GALILEO_OUTL(val, port) \ do { \ - *(volatile unsigned int *) GALILEO_REG(port) = (port); \ + *(volatile unsigned int *) GALILEO_REG(port) = (val); \ } while (0) -#define GALILEO_T0EXP 0x0100 +#define GALILEO_INTR_T0EXP (1 << 8) +#define GALILEO_INTR_RETRY_CTR (1 << 20) + #define GALILEO_ENTC0 0x01 #define GALILEO_SELTC0 0x02 @@ -86,5 +96,21 @@ do { \ GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) | \ (PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS) +#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000)) +# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */ +# define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */ +# define COBALT_LED_WEB (1 << 2) /* RaQ */ +# define COBALT_LED_POWER_OFF (1 << 3) /* RaQ */ +# define COBALT_LED_RESET 0x0f + +#define COBALT_KEY_PORT ((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK) +# define COBALT_KEY_CLEAR (1 << 1) +# define COBALT_KEY_LEFT (1 << 2) +# define COBALT_KEY_UP (1 << 3) +# define COBALT_KEY_DOWN (1 << 4) +# define COBALT_KEY_RIGHT (1 << 5) +# define COBALT_KEY_ENTER (1 << 6) +# define COBALT_KEY_SELECT (1 << 7) +# define COBALT_KEY_MASK 0xfe #endif /* __ASM_COBALT_H */ |
