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authorAndi Kleen <ak@suse.de>2006-06-26 13:56:13 +0200
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-26 10:48:14 -0700
commit240cd6a80642da528bfa382ec2ae4e3cb8991ea7 (patch)
tree6c24052ea167a2fd7e0be93c167e9e7da5bddd2b /include/asm-i386
parentfaee9a5dc9d8399cc3b1b8e18b6d7ff7b17f1af1 (diff)
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op-kernel-dev-240cd6a80642da528bfa382ec2ae4e3cb8991ea7.tar.gz
[PATCH] i386/x86-64: Emulate CPUID4 on AMD
Intel systems report the cache level data from CPUID 4 in sysfs. Add a CPUID 4 emulation for AMD CPUs to report the same information for them. This allows programs to read this information in a uniform way. The AMD way to report this is less flexible so some assumptions are hardcoded (e.g. no L3) Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-i386')
-rw-r--r--include/asm-i386/processor.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h
index 0c83cf1..b796210 100644
--- a/include/asm-i386/processor.h
+++ b/include/asm-i386/processor.h
@@ -112,6 +112,7 @@ extern char ignore_fpu_irq;
extern void identify_cpu(struct cpuinfo_x86 *);
extern void print_cpu_info(struct cpuinfo_x86 *);
extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
+extern unsigned short num_cache_leaves;
#ifdef CONFIG_X86_HT
extern void detect_ht(struct cpuinfo_x86 *c);
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