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| author | Andi Kleen <ak@suse.de> | 2007-04-02 12:14:12 +0200 |
|---|---|---|
| committer | Andi Kleen <andi@basil.nowhere.org> | 2007-04-02 12:14:12 +0200 |
| commit | 3556ddfa9284a86a59a9b78fe5894430f6ab4eef (patch) | |
| tree | f85b5acde48b6ffa7f1c9abbb3ea2ff4a2e92b4b /include/asm-i386 | |
| parent | 2e175a90047a2dbc76fde169c990164895b25dfc (diff) | |
| download | op-kernel-dev-3556ddfa9284a86a59a9b78fe5894430f6ab4eef.zip op-kernel-dev-3556ddfa9284a86a59a9b78fe5894430f6ab4eef.tar.gz | |
[PATCH] x86-64: Disable local APIC timer use on AMD systems with C1E
AMD dual core laptops with C1E do not run the APIC timer correctly
when they go idle. Previously the code assumed this only happened
on C2 or deeper. But not all of these systems report support C2.
Use a AMD supplied snippet to detect C1E being enabled and then disable
local apic timer use.
This supercedes an earlier workaround using DMI detection of specific systems.
Thanks to Mark Langsdorf for the detection snippet.
Signed-off-by: Andi Kleen <ak@suse.de>
Diffstat (limited to 'include/asm-i386')
| -rw-r--r-- | include/asm-i386/cpufeature.h | 1 | ||||
| -rw-r--r-- | include/asm-i386/msr.h | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h index 3f92b94..d1b8e4a 100644 --- a/include/asm-i386/cpufeature.h +++ b/include/asm-i386/cpufeature.h @@ -75,6 +75,7 @@ #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ +#define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ diff --git a/include/asm-i386/msr.h b/include/asm-i386/msr.h index ec3b680..2ad3f30 100644 --- a/include/asm-i386/msr.h +++ b/include/asm-i386/msr.h @@ -275,6 +275,8 @@ static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) #define MSR_K7_FID_VID_CTL 0xC0010041 #define MSR_K7_FID_VID_STATUS 0xC0010042 +#define MSR_K8_ENABLE_C1E 0xC0010055 + /* extended feature register */ #define MSR_EFER 0xc0000080 |
