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| author | Len Brown <len.brown@intel.com> | 2006-01-07 03:50:18 -0500 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2006-01-07 03:50:18 -0500 |
| commit | ed03f430cdc8c802652467e9097606fedc2c7abc (patch) | |
| tree | 30941ec1e6f93e99358fefe18175e5dd800a4379 /include/asm-i386/bugs.h | |
| parent | ed349a8a0a780ed27e2a765f16cee54d9b63bfee (diff) | |
| parent | 6f957eaf79356a32e838f5f262ee9a60544b1d5b (diff) | |
| download | op-kernel-dev-ed03f430cdc8c802652467e9097606fedc2c7abc.zip op-kernel-dev-ed03f430cdc8c802652467e9097606fedc2c7abc.tar.gz | |
Pull pnpacpi into acpica branch
Diffstat (limited to 'include/asm-i386/bugs.h')
| -rw-r--r-- | include/asm-i386/bugs.h | 23 |
1 files changed, 1 insertions, 22 deletions
diff --git a/include/asm-i386/bugs.h b/include/asm-i386/bugs.h index ea54540..50233e0 100644 --- a/include/asm-i386/bugs.h +++ b/include/asm-i386/bugs.h @@ -8,9 +8,6 @@ * <rreilova@ececs.uc.edu> * - Channing Corn (tests & fixes), * - Andrew D. Balsa (code cleanup). - * - * Pentium III FXSR, SSE support - * Gareth Hughes <gareth@valinux.com>, May 2000 */ /* @@ -76,25 +73,7 @@ static void __init check_fpu(void) return; } -/* Enable FXSR and company _before_ testing for FP problems. */ - /* - * Verify that the FXSAVE/FXRSTOR data will be 16-byte aligned. - */ - if (offsetof(struct task_struct, thread.i387.fxsave) & 15) { - extern void __buggy_fxsr_alignment(void); - __buggy_fxsr_alignment(); - } - if (cpu_has_fxsr) { - printk(KERN_INFO "Enabling fast FPU save and restore... "); - set_in_cr4(X86_CR4_OSFXSR); - printk("done.\n"); - } - if (cpu_has_xmm) { - printk(KERN_INFO "Enabling unmasked SIMD FPU exception support... "); - set_in_cr4(X86_CR4_OSXMMEXCPT); - printk("done.\n"); - } - +/* trap_init() enabled FXSR and company _before_ testing for FP problems here. */ /* Test for the divl bug.. */ __asm__("fninit\n\t" "fldl %1\n\t" |
