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authorAndi Kleen <ak@suse.de>2005-09-12 18:49:24 +0200
committerLinus Torvalds <torvalds@g5.osdl.org>2005-09-12 10:49:58 -0700
commit2b4a08150e0ce2f6eb5d0987fdfe3524ec799313 (patch)
treeae4d69033fa3e1e64485433bec8e496fc498ca8f /include/asm-generic
parent165aeb82848c81ee1774f8defc74df4341e9184b (diff)
downloadop-kernel-dev-2b4a08150e0ce2f6eb5d0987fdfe3524ec799313.zip
op-kernel-dev-2b4a08150e0ce2f6eb5d0987fdfe3524ec799313.tar.gz
[PATCH] x86-64: Increase TLB flush array size
The generic TLB flush functions kept upto 506 pages per CPU to avoid too frequent IPIs. This value was done for the L1 cache of older x86 CPUs, but with modern CPUs it does not make much sense anymore. TLB flushing is slow enough that using the L2 cache is fine. This patch increases the flush array on x86-64 to cache 5350 pages. That is roughly 20MB with 4K pages. It speeds up large munmaps in multithreaded processes on SMP considerably. The cost is roughly 42k of memory per CPU, which is reasonable. I only increased it on x86-64 for now, but it would probably make sense to increase it everywhere. Embedded architectures with SMP may keep it smaller to save some memory per CPU. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-generic')
-rw-r--r--include/asm-generic/tlb.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/include/asm-generic/tlb.h b/include/asm-generic/tlb.h
index faff403..7d02983 100644
--- a/include/asm-generic/tlb.h
+++ b/include/asm-generic/tlb.h
@@ -23,7 +23,11 @@
* and page free order so much..
*/
#ifdef CONFIG_SMP
- #define FREE_PTE_NR 506
+ #ifdef ARCH_FREE_PTR_NR
+ #define FREE_PTR_NR ARCH_FREE_PTR_NR
+ #else
+ #define FREE_PTE_NR 506
+ #endif
#define tlb_fast_mode(tlb) ((tlb)->nr == ~0U)
#else
#define FREE_PTE_NR 1
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