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authorWill Deacon <will.deacon@arm.com>2013-09-03 10:44:00 +0100
committerWill Deacon <will.deacon@arm.com>2014-10-20 18:49:17 +0100
commit9439eb3ab9d1ece6e4ad7baaa4a7f534f9b9dab0 (patch)
treee0c055ab3595d0f6f865f6aa2bbb0c6d51442adb /include/asm-generic
parentf114040e3ea6e07372334ade75d1ee0775c355e1 (diff)
downloadop-kernel-dev-9439eb3ab9d1ece6e4ad7baaa4a7f534f9b9dab0.zip
op-kernel-dev-9439eb3ab9d1ece6e4ad7baaa4a7f534f9b9dab0.tar.gz
asm-generic: io: implement relaxed accessor macros as conditional wrappers
{read,write}{b,w,l,q}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds wrappers to asm-generic so that drivers can rely on the relaxed accessors being available, even if they don't always provide weaker ordering guarantees. Since some architectures both include asm-generic/io.h and define some relaxed accessors, the definitions here are conditional for the time being. Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'include/asm-generic')
-rw-r--r--include/asm-generic/io.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index b8fdc57..fc8dc0e 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -53,18 +53,27 @@ static inline u32 __raw_readl(const volatile void __iomem *addr)
#endif
#define readb __raw_readb
+#ifndef readb_relaxed
+#define readb_relaxed readb
+#endif
#define readw readw
static inline u16 readw(const volatile void __iomem *addr)
{
return __le16_to_cpu(__raw_readw(addr));
}
+#ifndef readw_relaxed
+#define readw_relaxed readw
+#endif
#define readl readl
static inline u32 readl(const volatile void __iomem *addr)
{
return __le32_to_cpu(__raw_readl(addr));
}
+#ifndef readl_relaxed
+#define readl_relaxed readl
+#endif
#ifndef __raw_writeb
static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
@@ -88,8 +97,19 @@ static inline void __raw_writel(u32 b, volatile void __iomem *addr)
#endif
#define writeb __raw_writeb
+#ifndef writeb_relaxed
+#define writeb_relaxed writeb
+#endif
+
#define writew(b,addr) __raw_writew(__cpu_to_le16(b),addr)
+#ifndef writew_relaxed
+#define writew_relaxed writew
+#endif
+
#define writel(b,addr) __raw_writel(__cpu_to_le32(b),addr)
+#ifndef writel_relaxed
+#define writel_relaxed writel
+#endif
#ifdef CONFIG_64BIT
#ifndef __raw_readq
@@ -104,6 +124,9 @@ static inline u64 readq(const volatile void __iomem *addr)
{
return __le64_to_cpu(__raw_readq(addr));
}
+#ifndef readq_relaxed
+#define readq_relaxed readq
+#endif
#ifndef __raw_writeq
static inline void __raw_writeq(u64 b, volatile void __iomem *addr)
@@ -113,6 +136,9 @@ static inline void __raw_writeq(u64 b, volatile void __iomem *addr)
#endif
#define writeq(b, addr) __raw_writeq(__cpu_to_le64(b), addr)
+#ifndef writeq_relaxed
+#define writeq_relaxed writeq
+#endif
#endif /* CONFIG_64BIT */
#ifndef PCI_IOBASE
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