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authorSonic Zhang <sonic.zhang@analog.com>2008-02-02 16:31:00 +0800
committerBryan Wu <bryan.wu@analog.com>2008-02-02 16:31:00 +0800
commit8b01eaff4fdf39d23d53288fd1a3e74fef136145 (patch)
tree819a0e86598a75860fc2ed0c23a51f02957cee6c /include/asm-blackfin
parent83d9cde08b72233d113e31ab93b6b56151be8719 (diff)
downloadop-kernel-dev-8b01eaff4fdf39d23d53288fd1a3e74fef136145.zip
op-kernel-dev-8b01eaff4fdf39d23d53288fd1a3e74fef136145.tar.gz
[Blackfin] arch: Enable UART2 and UART3 for bf548
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin')
-rw-r--r--include/asm-blackfin/mach-bf548/dma.h4
-rw-r--r--include/asm-blackfin/mach-bf548/irq.h8
2 files changed, 12 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h
index 4d97d3a..46ff31f 100644
--- a/include/asm-blackfin/mach-bf548/dma.h
+++ b/include/asm-blackfin/mach-bf548/dma.h
@@ -51,9 +51,13 @@
#define CH_PIXC_OVERLAY 16
#define CH_PIXC_OUTPUT 17
#define CH_SPORT2_RX 18
+#define CH_UART2_RX 18
#define CH_SPORT2_TX 19
+#define CH_UART2_TX 19
#define CH_SPORT3_RX 20
+#define CH_UART3_RX 20
#define CH_SPORT3_TX 21
+#define CH_UART3_TX 21
#define CH_SDH 22
#define CH_NFC 22
#define CH_SPI2 23
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
index c34507a..ad380d1 100644
--- a/include/asm-blackfin/mach-bf548/irq.h
+++ b/include/asm-blackfin/mach-bf548/irq.h
@@ -99,9 +99,13 @@ Events (highest priority) EMU 0
#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
+#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
+#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
+#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
+#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
@@ -421,9 +425,13 @@ Events (highest priority) EMU 0
/* IAR4 BIT FILEDS */
#define IRQ_CAN0_ERR_POS 0
#define IRQ_SPORT2_RX_POS 4
+#define IRQ_UART2_RX_POS 4
#define IRQ_SPORT2_TX_POS 8
+#define IRQ_UART2_TX_POS 8
#define IRQ_SPORT3_RX_POS 12
+#define IRQ_UART3_RX_POS 12
#define IRQ_SPORT3_TX_POS 16
+#define IRQ_UART3_TX_POS 16
#define IRQ_EPPI1_POS 20
#define IRQ_EPPI2_POS 24
#define IRQ_SPI1_POS 28
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