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| author | Mike Frysinger <vapier.adi@gmail.com> | 2008-04-23 08:23:51 +0800 |
|---|---|---|
| committer | Bryan Wu <cooloney@kernel.org> | 2008-04-23 08:23:51 +0800 |
| commit | 0e184c6b4feba9640c85811a7929d18f4491ddb0 (patch) | |
| tree | 076d8ef2ca5e454a2f20637ad8d528cc85938503 /include/asm-blackfin/cplb.h | |
| parent | 53eabf046b2837647f186f0cba085ce7a43bd7ce (diff) | |
| download | op-kernel-dev-0e184c6b4feba9640c85811a7929d18f4491ddb0.zip op-kernel-dev-0e184c6b4feba9640c85811a7929d18f4491ddb0.tar.gz | |
[Blackfin] arch: relocate MAX_SWITCH_{D,I}_CPLBS from the header to the file where it actually gets used.
relocate MAX_SWITCH_{D,I}_CPLBS from the header to the file
where it actually gets used. this way when we change
CONFIG_MEM_SIZE in our kconfig, we only rebuild one or two files
rather than a whole bunch that implicitly include cplb.h.
this will also remove the ability to clear the swapcount on
the fly, but i really dont think that functionality is important.
ultimate goal is for CONFIG_MEM_SIZE to go away and calculate
this value on the fly based on what u-boot programmed for us.
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include/asm-blackfin/cplb.h')
| -rw-r--r-- | include/asm-blackfin/cplb.h | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h index 654375c..5b0da9a 100644 --- a/include/asm-blackfin/cplb.h +++ b/include/asm-blackfin/cplb.h @@ -74,32 +74,6 @@ #define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M) -/* -* Number of required data CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 16 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Data Memory -* possibly 1 for L2 Data Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -* 1 for ASYNC Memory -*/ - - -#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \ - + ASYNC_MEMORY_CPLB_COVERAGE) * 2) - -/* -* Number of required instruction CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 12 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Instruction Memory -* possibly 1 for L2 Instruction Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -*/ - -#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2) - - #define CPLB_ENABLE_ICACHE_P 0 #define CPLB_ENABLE_DCACHE_P 1 #define CPLB_ENABLE_DCACHE2_P 2 |
