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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2005-11-09 14:57:32 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-11-09 14:57:32 +0000
commitbe6eb9b79f99e652a0827a475c4daa02ecef221f (patch)
treefab14db6e48cc394fed9a6ae813a0add6f202b20 /include/asm-arm
parentc906107bb72b7bd5ecfc98cc807bdb8f34d17501 (diff)
parent97a63ecff4bd06da5d8feb8c0394a4d020f2d34d (diff)
downloadop-kernel-dev-be6eb9b79f99e652a0827a475c4daa02ecef221f.zip
op-kernel-dev-be6eb9b79f99e652a0827a475c4daa02ecef221f.tar.gz
Merge with ARM SMP tree
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-realview/entry-macro.S11
-rw-r--r--include/asm-arm/arch-realview/irqs.h3
-rw-r--r--include/asm-arm/arch-realview/platform.h5
3 files changed, 16 insertions, 3 deletions
diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S
index 4df469b..6288fad 100644
--- a/include/asm-arm/arch-realview/entry-macro.S
+++ b/include/asm-arm/arch-realview/entry-macro.S
@@ -61,3 +61,14 @@
strcc \irqstat, [\base, #GIC_CPU_EOI]
cmpcs \irqnr, \irqnr
.endm
+
+ /* As above, this assumes that irqstat and base are preserved.. */
+
+ .macro test_for_ltirq, irqnr, irqstat, base, tmp
+ bic \irqnr, \irqstat, #0x1c00
+ mov \tmp, #0
+ cmp \irqnr, #29
+ moveq \tmp, #1
+ streq \irqstat, [\base, #GIC_CPU_EOI]
+ cmp \tmp, #0
+ .endm
diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h
index ff37649..c16223c 100644
--- a/include/asm-arm/arch-realview/irqs.h
+++ b/include/asm-arm/arch-realview/irqs.h
@@ -21,6 +21,9 @@
#include <asm/arch/platform.h>
+#define IRQ_LOCALTIMER 29
+#define IRQ_LOCALWDOG 30
+
/*
* IRQ interrupts definitions are the same the INT definitions
* held within platform.h
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h
index aef9b36..18d7c18 100644
--- a/include/asm-arm/arch-realview/platform.h
+++ b/include/asm-arm/arch-realview/platform.h
@@ -209,6 +209,8 @@
#else
#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */
#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
+#define REALVIEW_TWD_BASE 0x10100700
+#define REALVIEW_TWD_SIZE 0x00000100
#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
#endif
#define REALVIEW_SMC_BASE 0x10080000 /* SMC */
@@ -305,9 +307,6 @@
#define INT_TSPENINT 30 /* Touchscreen pen */
#define INT_TSKPADINT 31 /* Touchscreen keypad */
#else
-#define INT_LOCALTIMER 29
-#define INT_LOCALWDOG 30
-
#define INT_AACI 0
#define INT_TIMERINT0_1 1
#define INT_TIMERINT2_3 2
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