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| author | Lennert Buytenhek <buytenh@wantstofly.org> | 2006-04-02 00:07:39 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-04-02 00:07:39 +0100 |
| commit | 23759dc6430428897a36c4d493f611eca55c9481 (patch) | |
| tree | c62050927599b36ed223753c35fd737e3c0c6762 /include/asm-arm/pgtable.h | |
| parent | d3f4c571b6e596f9d39c596426269006a309d3b8 (diff) | |
| download | op-kernel-dev-23759dc6430428897a36c4d493f611eca55c9481.zip op-kernel-dev-23759dc6430428897a36c4d493f611eca55c9481.tar.gz | |
[ARM] 3439/2: xsc3: add I/O coherency support
Patch from Lennert Buytenhek
This patch adds support for the I/O coherent cache available on the
xsc3. The approach is to provide a simple API to determine whether the
chipset supports coherency by calling arch_is_coherent() and then
setting the appropriate system memory PTE and PMD bits. In addition,
we call this API on dma_alloc_coherent() and dma_map_single() calls.
A generic version exists that will compile out all the coherency-related
code that is not needed on the majority of ARM systems.
Note that we do not check for coherency in the dma_alloc_writecombine()
function as that still requires a special PTE setting. We also don't
touch dma_mmap_coherent() as that is a special ARM-only API that is by
definition only used on non-coherent system.
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/pgtable.h')
| -rw-r--r-- | include/asm-arm/pgtable.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h index e595ae2..e85c08d 100644 --- a/include/asm-arm/pgtable.h +++ b/include/asm-arm/pgtable.h @@ -156,6 +156,7 @@ extern void __pgd_error(const char *file, int line, unsigned long val); #define L_PTE_WRITE (1 << 5) #define L_PTE_EXEC (1 << 6) #define L_PTE_DIRTY (1 << 7) +#define L_PTE_COHERENT (1 << 9) /* I/O coherent (xsc3) */ #define L_PTE_SHARED (1 << 10) /* shared between CPUs (v6) */ #define L_PTE_ASID (1 << 11) /* non-global (use ASID, v6) */ |
