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authorLv Zheng <lv.zheng@intel.com>2017-06-05 16:38:26 +0800
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2017-06-12 14:58:37 +0200
commitb8355bcac2534fc3faad25ec25c1972582469507 (patch)
tree3e0bbda81e70f93e73627b3fd5063160740cdb89 /include/acpi/actbl1.h
parent4a8a6058a9099560a421ab3850d4889765c512b3 (diff)
downloadop-kernel-dev-b8355bcac2534fc3faad25ec25c1972582469507.zip
op-kernel-dev-b8355bcac2534fc3faad25ec25c1972582469507.tar.gz
ACPICA: Tables: Add PPTT table definitions
ACPICA commit c27465d07fd008ba71c1f687b2715267701bc8ad This patch adds PPTT (Processor Properties Topology Table, defined in ACPI spec 6.2) support in ACPICA core, including table definitions expressed in C structures and macros. Lv Zheng. Link: https://github.com/acpica/acpica/commit/c27465d0 Signed-off-by: Lv Zheng <lv.zheng@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'include/acpi/actbl1.h')
-rw-r--r--include/acpi/actbl1.h80
1 files changed, 80 insertions, 0 deletions
diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index 87a12e1..f57e94c 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -69,6 +69,7 @@
#define ACPI_SIG_HEST "HEST" /* Hardware Error Source Table */
#define ACPI_SIG_MADT "APIC" /* Multiple APIC Description Table */
#define ACPI_SIG_MSCT "MSCT" /* Maximum System Characteristics Table */
+#define ACPI_SIG_PPTT "PPTT" /* Processor Properties Topology Table */
#define ACPI_SIG_SBST "SBST" /* Smart Battery Specification Table */
#define ACPI_SIG_SLIT "SLIT" /* System Locality Distance Information Table */
#define ACPI_SIG_SRAT "SRAT" /* System Resource Affinity Table */
@@ -1265,6 +1266,85 @@ struct acpi_nfit_flush_address {
/*******************************************************************************
*
+ * PPTT - Processor Properties Topology Table (ACPI 6.2)
+ * Version 1
+ *
+ ******************************************************************************/
+
+struct acpi_table_pptt {
+ struct acpi_table_header header; /* Common ACPI table header */
+};
+
+/* Values for Type field above */
+
+enum acpi_pptt_type {
+ ACPI_PPTT_TYPE_PROCESSOR = 0,
+ ACPI_PPTT_TYPE_CACHE = 1,
+ ACPI_PPTT_TYPE_ID = 2,
+ ACPI_PPTT_TYPE_RESERVED = 3
+};
+
+/* 0: Processor Hierarchy Node Structure */
+
+struct acpi_pptt_processor {
+ struct acpi_subtable_header header;
+ u16 reserved;
+ u32 flags;
+ u32 parent;
+ u32 acpi_processor_id;
+ u32 number_of_priv_resources;
+};
+
+/* Flags */
+
+#define ACPI_PPTT_PHYSICAL_PACKAGE (1) /* Physical package */
+#define ACPI_PPTT_ACPI_PROCESSOR_ID_VALID (2) /* ACPI Processor ID valid */
+
+/* 1: Cache Type Structure */
+
+struct acpi_pptt_cache {
+ struct acpi_subtable_header header;
+ u16 reserved;
+ u32 flags;
+ u32 next_level_of_cache;
+ u32 size;
+ u32 number_of_sets;
+ u8 associativity;
+ u8 attributes;
+ u16 line_size;
+};
+
+/* Flags */
+
+#define ACPI_PPTT_SIZE_PROPERTY_VALID (1) /* Physical property valid */
+#define ACPI_PPTT_NUMBER_OF_SETS_VALID (1<<1) /* Number of sets valid */
+#define ACPI_PPTT_ASSOCIATIVITY_VALID (1<<2) /* Associativity valid */
+#define ACPI_PPTT_ALLOCATION_TYPE_VALID (1<<3) /* Allocation type valid */
+#define ACPI_PPTT_CACHE_TYPE_VALID (1<<4) /* Cache type valid */
+#define ACPI_PPTT_WRITE_POLICY_VALID (1<<5) /* Write policy valid */
+#define ACPI_PPTT_LINE_SIZE_VALID (1<<6) /* Line size valid */
+
+/* Masks for Attributes */
+
+#define ACPI_PPTT_MASK_ALLOCATION_TYPE (0x03) /* Allocation type */
+#define ACPI_PPTT_MASK_CACHE_TYPE (0x0C) /* Cache type */
+#define ACPI_PPTT_MASK_WRITE_POLICY (0x10) /* Write policy */
+
+/* 2: ID Structure */
+
+struct acpi_pptt_id {
+ struct acpi_subtable_header header;
+ u16 reserved;
+ u32 vendor_id;
+ u64 level1_id;
+ u64 level2_id;
+ u16 major_rev;
+ u16 minor_rev;
+ u16 spin_rev;
+};
+
+/*******************************************************************************
+ *
* SBST - Smart Battery Specification Table
* Version 1
*
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