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authorLinus Torvalds <torvalds@linux-foundation.org>2013-04-03 16:15:17 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2013-04-03 16:15:17 -0700
commit66ade474237745a57b7e87da9a93c7ec69fd52bb (patch)
treea3e08728d8584fde056ec51f4b2249e3dd6032c5 /fs
parentcbfa0e7204159515e63321142bcc2d6dcb854045 (diff)
parent4e1db26a0b42e2b6e27c05d68adcc01709c2eed2 (diff)
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op-kernel-dev-66ade474237745a57b7e87da9a93c7ec69fd52bb.tar.gz
Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM fixes from Russell King: "Another round of ARM fixes, which include: - Fixing a problem with LPAE mapping sections - Reporting of some hwcaps on Krait CPUs - Avoiding repetitive warnings in the breakpoint code - Fixing a build error noticed on Dove platforms with PJ4 CPUs - Fix masking of level 2 cache revision. - Fixing timer-based udelay() - A larger fix for an erratum causing people major grief with Cortex A15 CPUs" * 'fixes' of git://git.linaro.org/people/rmk/linux-arm: ARM: 7690/1: mm: fix CONFIG_LPAE typos ARM: 7689/1: add unwind annotations to ftrace asm ARM: 7685/1: delay: use private ticks_per_jiffy field for timer-based delay ops ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations) ARM: 7682/1: cache-l2x0: fix masking of RTL revision numbering and set_debug init ARM: iWMMXt: always enable iWMMXt support with PJ4 CPUs ARM: 7681/1: hw_breakpoint: use warn_once to avoid spam from reset_ctrl_regs() ARM: 7678/1: Work around faulty ISAR0 register in some Krait CPUs ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register ARM: 7679/1: Clear IDIVT hwcap if CONFIG_ARM_THUMB=n ARM: 7677/1: LPAE: Fix mapping in alloc_init_section for unaligned addresses ARM: KVM: vgic: take distributor lock on sync_hwstate path ARM: KVM: vgic: force EOIed LRs to the empty state
Diffstat (limited to 'fs')
0 files changed, 0 insertions, 0 deletions
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