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authorDave Martin <Dave.Martin@arm.com>2017-10-31 15:51:10 +0000
committerWill Deacon <will.deacon@arm.com>2017-11-03 15:24:17 +0000
commit2e0f2478ea37eba945bee007884a2988b8f7d332 (patch)
treeeefdac015c0ee8702fefbdc99e3bf941d8456084 /drivers
parent8f1eec57cdccd17faeaf7f593505124376340fd0 (diff)
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op-kernel-dev-2e0f2478ea37eba945bee007884a2988b8f7d332.tar.gz
arm64/sve: Probe SVE capabilities and usable vector lengths
This patch uses the cpufeatures framework to determine common SVE capabilities and vector lengths, and configures the runtime SVE support code appropriately. ZCR_ELx is not really a feature register, but it is convenient to use it as a template for recording the maximum vector length supported by a CPU, using the LEN field. This field is similar to a feature field in that it is a contiguous bitfield for which we want to determine the minimum system-wide value. This patch adds ZCR as a pseudo-register in cpuinfo/cpufeatures, with appropriate custom code to populate it. Finding the minimum supported value of the LEN field is left to the cpufeatures framework in the usual way. The meaning of ID_AA64ZFR0_EL1 is not architecturally defined yet, so for now we just require it to be zero. Note that much of this code is dormant and SVE still won't be used yet, since system_supports_sve() remains hardwired to false. Signed-off-by: Dave Martin <Dave.Martin@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
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