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authorDavid S. Miller <davem@davemloft.net>2017-07-05 09:23:53 +0100
committerDavid S. Miller <davem@davemloft.net>2017-07-05 09:23:53 +0100
commit0e72582270c07850b92cac351c8b97d4f9c123b9 (patch)
tree481610b7bace6165ba28cfe1c54eeb9151d8133b /drivers
parenta778427efc67490b6ee7ea4593065dede4445fb6 (diff)
parent371444764b9882d754d1e67dd212c932359a2293 (diff)
downloadop-kernel-dev-0e72582270c07850b92cac351c8b97d4f9c123b9.zip
op-kernel-dev-0e72582270c07850b92cac351c8b97d4f9c123b9.tar.gz
Merge branch 'phy-dp83867-workaround-incorrect-RX_CTRL-pin-strap'
Sekhar Nori says: ==================== net: phy: dp83867: workaround incorrect RX_CTRL pin strap This patch series adds workaround for incorrect RX_CTRL pin strap setting that can be found on some TI boards. This is required to be complaint to PHY datamanual specification. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/phy/dp83867.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index b57f20e..c1ab976 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -91,6 +91,7 @@ struct dp83867_private {
int fifo_depth;
int io_impedance;
int port_mirroring;
+ bool rxctrl_strap_quirk;
};
static int dp83867_ack_interrupt(struct phy_device *phydev)
@@ -164,6 +165,9 @@ static int dp83867_of_init(struct phy_device *phydev)
else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
+ dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
+ "ti,dp83867-rxctrl-strap-quirk");
+
ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
&dp83867->rx_id_delay);
if (ret &&
@@ -214,6 +218,13 @@ static int dp83867_config_init(struct phy_device *phydev)
dp83867 = (struct dp83867_private *)phydev->priv;
}
+ /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
+ if (dp83867->rxctrl_strap_quirk) {
+ val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
+ val &= ~BIT(7);
+ phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
+ }
+
if (phy_interface_is_rgmii(phydev)) {
val = phy_read(phydev, MII_DP83867_PHYCTRL);
if (val < 0)
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