diff options
| author | Alexander Duyck <alexander.h.duyck@intel.com> | 2009-05-26 13:51:05 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-05-26 20:35:06 -0700 |
| commit | cbe7a81a7370e2c4560b48e42e741bd1476bc700 (patch) | |
| tree | 06909d59a09cac98dcfd6221b67a6bcf3bf6e6ff /drivers | |
| parent | 3ea73afafb8cd237a823ec5d0a0a2f2396b03b33 (diff) | |
| download | op-kernel-dev-cbe7a81a7370e2c4560b48e42e741bd1476bc700.zip op-kernel-dev-cbe7a81a7370e2c4560b48e42e741bd1476bc700.tar.gz | |
igb/e1000e: update PSSR_MDIX value to reflect correct bit
The phy port status register has the MDI-X status bit on bit 11, not bit 3
as is currently setup in the define. This patch corrects that so the
correct bit is checked on igp PHY types.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Acked-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/e1000e/hw.h | 2 | ||||
| -rw-r--r-- | drivers/net/igb/e1000_phy.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h index d8b8229..6cdb703 100644 --- a/drivers/net/e1000e/hw.h +++ b/drivers/net/e1000e/hw.h @@ -253,7 +253,7 @@ enum e1e_registers { #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 -#define IGP01E1000_PSSR_MDIX 0x0008 +#define IGP01E1000_PSSR_MDIX 0x0800 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 diff --git a/drivers/net/igb/e1000_phy.h b/drivers/net/igb/e1000_phy.h index 3228a86..ebe4b61 100644 --- a/drivers/net/igb/e1000_phy.h +++ b/drivers/net/igb/e1000_phy.h @@ -80,7 +80,7 @@ s32 igb_phy_init_script_igp3(struct e1000_hw *hw); #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 -#define IGP01E1000_PSSR_MDIX 0x0008 +#define IGP01E1000_PSSR_MDIX 0x0800 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 #define IGP02E1000_PHY_CHANNEL_NUM 4 |
