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| author | Sergei Shtylyov <sshtylyov@ru.mvista.com> | 2007-07-03 22:28:35 +0200 |
|---|---|---|
| committer | Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> | 2007-07-03 22:28:35 +0200 |
| commit | 96dcc08b0c6b730474469b10ed5eeda06e617deb (patch) | |
| tree | 524e9bfe6800a7f6ce42d618d9c450359ac76da9 /drivers | |
| parent | 783353b1d3d1ed3ae4a0bd4ea4557bd4d77aa04e (diff) | |
| download | op-kernel-dev-96dcc08b0c6b730474469b10ed5eeda06e617deb.zip op-kernel-dev-96dcc08b0c6b730474469b10ed5eeda06e617deb.tar.gz | |
hpt366: use correct enablebits for HPT36x
The HPT36x chips finally turned out to have the channel enable bits -- however,
badly implemented. Make use of them despite it's probably only going to burden
the driver's code -- assuming both channels are always enabled by the HighPoint
BIOS anyway...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Acked-by: Linas Vepstas <linas@austin.ibm.com>
Cc: michal.kepien@poczta.onet.pl
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ide/pci/hpt366.c | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c index 4f8017a..c33d0b0 100644 --- a/drivers/ide/pci/hpt366.c +++ b/drivers/ide/pci/hpt366.c @@ -1,5 +1,5 @@ /* - * linux/drivers/ide/pci/hpt366.c Version 1.05 Jun 26, 2007 + * linux/drivers/ide/pci/hpt366.c Version 1.06 Jun 27, 2007 * * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> * Portions Copyright (C) 2001 Sun Microsystems, Inc. @@ -1514,18 +1514,28 @@ static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d) goto init_single; /* - * HPT36x chips are single channel and - * do not seem to have the channel enable bit... + * HPT36x chips have one channel per function and have + * both channel enable bits located differently and visible + * to both functions -- really stupid design decision... :-( + * Bit 4 is for the primary channel, bit 5 for the secondary. */ d->channels = 1; - d->enablebits[0].reg = 0; + d->enablebits[0].mask = d->enablebits[0].val = 0x10; if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) { - u8 pin1 = 0, pin2 = 0; + u8 mcr1 = 0, pin1 = 0, pin2 = 0; int ret; pci_set_drvdata(dev2, info[rev]); + /* + * Now we'll have to force both channels enabled if + * at least one of them has been enabled by BIOS... + */ + pci_read_config_byte(dev, 0x50, &mcr1); + if (mcr1 & 0x30) + pci_write_config_byte(dev, 0x50, mcr1 | 0x30); + pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1); pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2); if (pin1 != pin2 && dev->irq == dev2->irq) { |
