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| author | Hauke Mehrtens <hauke@hauke-m.de> | 2011-06-21 20:53:20 +0200 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2011-06-27 15:09:39 -0400 |
| commit | e913d468308be1cce7cc8e6e6e997d54a403ce64 (patch) | |
| tree | c621977bc0bc5a53ef559b89c19be528ab6b0cd8 /drivers | |
| parent | f9fc51365d0cf66d1f95f47618566f27177ecbbc (diff) | |
| download | op-kernel-dev-e913d468308be1cce7cc8e6e6e997d54a403ce64.zip op-kernel-dev-e913d468308be1cce7cc8e6e6e997d54a403ce64.tar.gz | |
ssb: fix ssb clock rate according to broadcom source
This fix was done according to si_clock_rate function in broadcom siutils.c
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ssb/main.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c index e568664..57b7b64 100644 --- a/drivers/ssb/main.c +++ b/drivers/ssb/main.c @@ -1002,8 +1002,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m) switch (plltype) { case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ if (m & SSB_CHIPCO_CLK_T6_MMASK) - return SSB_CHIPCO_CLK_T6_M0; - return SSB_CHIPCO_CLK_T6_M1; + return SSB_CHIPCO_CLK_T6_M1; + return SSB_CHIPCO_CLK_T6_M0; case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ |
