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| author | Alex Deucher <alexander.deucher@amd.com> | 2013-08-14 18:58:43 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-08-30 16:30:58 -0400 |
| commit | 773dc10a8acd28c19947b557094d4c1ec0043998 (patch) | |
| tree | 9feaf191907840e48eb5463bc6b75d19c637a488 /drivers | |
| parent | 6500fc0c9fd9a0c3cde1b498541a259d1ba078ba (diff) | |
| download | op-kernel-dev-773dc10a8acd28c19947b557094d4c1ec0043998.zip op-kernel-dev-773dc10a8acd28c19947b557094d4c1ec0043998.tar.gz | |
drm/radeon: enable mgcg on CIK
Now that the CP is no longer reset and cg is properly
disabled in when appropriate in the dpm code we can
now enable mgcg (medium grained clockgating).
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 6152169..630853b 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -2439,7 +2439,7 @@ int radeon_asic_init(struct radeon_device *rdev) rdev->num_crtc = 6; rdev->has_uvd = true; rdev->cg_flags = - /*RADEON_CG_SUPPORT_GFX_MGCG |*/ + RADEON_CG_SUPPORT_GFX_MGCG | RADEON_CG_SUPPORT_GFX_MGLS | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ RADEON_CG_SUPPORT_GFX_CGLS | @@ -2464,7 +2464,7 @@ int radeon_asic_init(struct radeon_device *rdev) if (rdev->family == CHIP_KAVERI) { rdev->num_crtc = 4; rdev->cg_flags = - /*RADEON_CG_SUPPORT_GFX_MGCG |*/ + RADEON_CG_SUPPORT_GFX_MGCG | RADEON_CG_SUPPORT_GFX_MGLS | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ RADEON_CG_SUPPORT_GFX_CGLS | @@ -2492,7 +2492,7 @@ int radeon_asic_init(struct radeon_device *rdev) } else { rdev->num_crtc = 2; rdev->cg_flags = - /*RADEON_CG_SUPPORT_GFX_MGCG |*/ + RADEON_CG_SUPPORT_GFX_MGCG | RADEON_CG_SUPPORT_GFX_MGLS | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ RADEON_CG_SUPPORT_GFX_CGLS | |
