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authorDarren Etheridge <detheridge@ti.com>2013-08-23 16:52:51 -0500
committerTomi Valkeinen <tomi.valkeinen@ti.com>2013-08-30 14:50:26 +0300
commit83edd73a9cfd03dad9052abec31d9fb16a28543d (patch)
treed6abaec3f18219c22a15ea40ac0a730f807b682c /drivers
parenta592d9fd63ca619ba4c15e8d83ec6c955eb18eaa (diff)
downloadop-kernel-dev-83edd73a9cfd03dad9052abec31d9fb16a28543d.zip
op-kernel-dev-83edd73a9cfd03dad9052abec31d9fb16a28543d.tar.gz
video: da8xx-fb: fixing timing off by one errors
The LCD controller represents some of the timing fields with a 0 in the register representing 1. This was not taken into account when these registers were being set. Interestingly enough not all of the LCDC controller timing registers implement this representation so carefully went through the technical reference manual to only "fix" the correct timings. Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/video/da8xx-fb.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
index 0a0983f..7dfa7a7 100644
--- a/drivers/video/da8xx-fb.c
+++ b/drivers/video/da8xx-fb.c
@@ -407,9 +407,9 @@ static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
u32 reg;
reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
- reg |= ((back_porch & 0xff) << 24)
- | ((front_porch & 0xff) << 16)
- | ((pulse_width & 0x3f) << 10);
+ reg |= (((back_porch-1) & 0xff) << 24)
+ | (((front_porch-1) & 0xff) << 16)
+ | (((pulse_width-1) & 0x3f) << 10);
lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
}
@@ -421,7 +421,7 @@ static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
reg |= ((back_porch & 0xff) << 24)
| ((front_porch & 0xff) << 16)
- | ((pulse_width & 0x3f) << 10);
+ | (((pulse_width-1) & 0x3f) << 10);
lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
}
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