diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2013-08-26 13:48:36 +0200 |
|---|---|---|
| committer | Viresh Kumar <viresh.kumar@linaro.org> | 2013-08-26 19:34:07 +0530 |
| commit | fae19b84724ff93c1ac59ce1eecc1411f8269d9e (patch) | |
| tree | ec3d8cbd4006c2c45e2afb5725683efc69fc39a3 /drivers | |
| parent | b192b910f3832793082c1a18262c4da0efe121ae (diff) | |
| download | op-kernel-dev-fae19b84724ff93c1ac59ce1eecc1411f8269d9e.zip op-kernel-dev-fae19b84724ff93c1ac59ce1eecc1411f8269d9e.tar.gz | |
cpufreq: imx6q: Fix clock enable balance
For changing the cpu frequency the i.MX6q has to be switched to some
intermediate clock during the PLL reprogramming. The driver tries
to be clever to keep the enable count correct but gets it wrong. If
the cpufreq is increased it calls clk_disable_unprepare twice
on pll2_pfd2_396m. This puts all other devices which get their clock
from pll2_pfd2_396m into a nonworking state.
Fix this by removing the clk enabling/disabling altogether since the
clk core will do this automatically during a reparent.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/cpufreq/imx6q-cpufreq.c | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c index e37cdae..2971d12 100644 --- a/drivers/cpufreq/imx6q-cpufreq.c +++ b/drivers/cpufreq/imx6q-cpufreq.c @@ -117,28 +117,11 @@ static int imx6q_set_target(struct cpufreq_policy *policy, * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it * - Disable pll2_pfd2_396m_clk */ - clk_prepare_enable(pll2_pfd2_396m_clk); clk_set_parent(step_clk, pll2_pfd2_396m_clk); clk_set_parent(pll1_sw_clk, step_clk); if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) { clk_set_rate(pll1_sys_clk, freqs.new * 1000); - /* - * If we are leaving 396 MHz set-point, we need to enable - * pll1_sys_clk and disable pll2_pfd2_396m_clk to keep - * their use count correct. - */ - if (freqs.old * 1000 <= clk_get_rate(pll2_pfd2_396m_clk)) { - clk_prepare_enable(pll1_sys_clk); - clk_disable_unprepare(pll2_pfd2_396m_clk); - } clk_set_parent(pll1_sw_clk, pll1_sys_clk); - clk_disable_unprepare(pll2_pfd2_396m_clk); - } else { - /* - * Disable pll1_sys_clk if pll2_pfd2_396m_clk is sufficient - * to provide the frequency. - */ - clk_disable_unprepare(pll1_sys_clk); } /* Ensure the arm clock divider is what we expect */ |
