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authorKomuro <komurojun-mbn@nifty.com>2008-04-20 14:32:34 +0900
committerJeff Garzik <jgarzik@redhat.com>2008-05-22 14:08:50 -0400
commit43fc63dceb8ff58c5ef0a30c70abd31336b5e8b4 (patch)
tree321d348e4bfe247b6d0df24b815a86abdb6dad90 /drivers
parentf7f312a0c7e7a1947cf193e0e94a257ad7742cb2 (diff)
downloadop-kernel-dev-43fc63dceb8ff58c5ef0a30c70abd31336b5e8b4.zip
op-kernel-dev-43fc63dceb8ff58c5ef0a30c70abd31336b5e8b4.tar.gz
xirc2ps_cs: re-initialize the multicast address in do_reset
keep bit7,8 of XIRCREG42_SWC1 in set_multicast_list. Signed-off-by: Komuro <komurojun-mbn@nifty.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/pcmcia/xirc2ps_cs.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/net/pcmcia/xirc2ps_cs.c b/drivers/net/pcmcia/xirc2ps_cs.c
index d041f83..f6c4698 100644
--- a/drivers/net/pcmcia/xirc2ps_cs.c
+++ b/drivers/net/pcmcia/xirc2ps_cs.c
@@ -1461,22 +1461,25 @@ static void
set_multicast_list(struct net_device *dev)
{
unsigned int ioaddr = dev->base_addr;
+ unsigned value;
SelectPage(0x42);
+ value = GetByte(XIRCREG42_SWC1) & 0xC0;
+
if (dev->flags & IFF_PROMISC) { /* snoop */
- PutByte(XIRCREG42_SWC1, 0x06); /* set MPE and PME */
+ PutByte(XIRCREG42_SWC1, value | 0x06); /* set MPE and PME */
} else if (dev->mc_count > 9 || (dev->flags & IFF_ALLMULTI)) {
- PutByte(XIRCREG42_SWC1, 0x02); /* set MPE */
+ PutByte(XIRCREG42_SWC1, value | 0x02); /* set MPE */
} else if (dev->mc_count) {
/* the chip can filter 9 addresses perfectly */
- PutByte(XIRCREG42_SWC1, 0x01);
+ PutByte(XIRCREG42_SWC1, value | 0x01);
SelectPage(0x40);
PutByte(XIRCREG40_CMD0, Offline);
set_addresses(dev);
SelectPage(0x40);
PutByte(XIRCREG40_CMD0, EnableRecv | Online);
} else { /* standard usage */
- PutByte(XIRCREG42_SWC1, 0x00);
+ PutByte(XIRCREG42_SWC1, value | 0x00);
}
SelectPage(0);
}
@@ -1722,6 +1725,7 @@ do_reset(struct net_device *dev, int full)
/* enable receiver and put the mac online */
if (full) {
+ set_multicast_list(dev);
SelectPage(0x40);
PutByte(XIRCREG40_CMD0, EnableRecv | Online);
}
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