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| author | Wenyou Yang <wenyou.yang@atmel.com> | 2015-08-06 18:16:46 +0800 |
|---|---|---|
| committer | Wim Van Sebroeck <wim@iguana.be> | 2015-09-09 21:38:29 +0200 |
| commit | 76534860f108b812926a4fbfbdadbfa9cdec89d0 (patch) | |
| tree | c8eccc6ed7907af62386a4b280b179d698819763 /drivers/watchdog/at91sam9_wdt.h | |
| parent | f8c33e9717150f7b8063d6d77a8ea90adad434e9 (diff) | |
| download | op-kernel-dev-76534860f108b812926a4fbfbdadbfa9cdec89d0.zip op-kernel-dev-76534860f108b812926a4fbfbdadbfa9cdec89d0.tar.gz | |
watchdog: add a driver to support SAMA5D4 watchdog timer
From SAMA5D4, the watchdog timer is upgrated with a new feature,
which is describled as in the datasheet, "WDT_MR can be written
until a LOCKMR command is issued in WDT_CR".
That is to say, as long as the bootstrap and u-boot don't issue
a LOCKMR command, WDT_MR can be written more than once in the driver.
So the SAMA5D4 watchdog driver's implementation is different from
the at91sam9260 watchdog driver implemented in file at91sam9_wdt.c.
The user application open the device file to enable the watchdog timer
hardware, and close to disable it, and set the watchdog timer timeout
by seting WDV and WDD fields of WDT_MR register, and ping the watchdog
by issuing WDRSTT command to WDT_CR register with hard-coded key.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Diffstat (limited to 'drivers/watchdog/at91sam9_wdt.h')
| -rw-r--r-- | drivers/watchdog/at91sam9_wdt.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/watchdog/at91sam9_wdt.h b/drivers/watchdog/at91sam9_wdt.h index c6fbb2e6..b79a83b 100644 --- a/drivers/watchdog/at91sam9_wdt.h +++ b/drivers/watchdog/at91sam9_wdt.h @@ -22,11 +22,13 @@ #define AT91_WDT_MR 0x04 /* Watchdog Mode Register */ #define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ +#define AT91_WDT_SET_WDV(x) ((x) & AT91_WDT_WDV) #define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ #define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ #define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ #define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ #define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ +#define AT91_WDT_SET_WDD(x) (((x) << 16) & AT91_WDT_WDD) #define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ #define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ |
