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authorTomi Valkeinen <tomi.valkeinen@ti.com>2011-08-22 13:16:24 +0300
committerTomi Valkeinen <tomi.valkeinen@ti.com>2011-09-30 16:16:41 +0300
commitb44e45825dbe30f32c770b98c38555b6bd331760 (patch)
treed465a3954443a86e6c0ee1e688b93b78b9c8cbaf /drivers/video
parent8d88767a4377171752c22ac39bcb2b505eb751da (diff)
downloadop-kernel-dev-b44e45825dbe30f32c770b98c38555b6bd331760.zip
op-kernel-dev-b44e45825dbe30f32c770b98c38555b6bd331760.tar.gz
OMAP: DSS2: HDMI: change regn definition
regn divider is currently programmed to the registers without change, but when calculating clock frequencies it is used as regn+1. To make this similar to how DSI handles the dividers this patch changes the regn value to be used as such for calculations, but the value programmed to registers is regn-1. This simplifies the clock frequency calculations, makes it similar to DSI, and also allows us to use regn value 0 as undefined. Cc: Mythri P K <mythripk@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/omap2/dss/hdmi.c6
-rw-r--r--drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c2
2 files changed, 4 insertions, 4 deletions
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index 52731b5..4752137b 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -60,7 +60,7 @@
#define OMAP_HDMI_TIMINGS_NB 34
-#define HDMI_DEFAULT_REGN 15
+#define HDMI_DEFAULT_REGN 16
#define HDMI_DEFAULT_REGM2 1
static struct {
@@ -426,7 +426,7 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
else
pi->regn = dssdev->clocks.hdmi.regn;
- refclk = clkin / (pi->regn + 1);
+ refclk = clkin / pi->regn;
/*
* multiplier is pixel_clk/ref_clk
@@ -452,7 +452,7 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
* is greater than 1000MHz
*/
pi->dcofreq = phy > 1000 * 100;
- pi->regsd = ((pi->regm * clkin / 10) / ((pi->regn + 1) * 250) + 5) / 10;
+ pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
/* Set the reference clock to sysclk reference */
pi->refsel = HDMI_REFSEL_SYSCLK;
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
index cb3a2d67..403c662 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
@@ -92,7 +92,7 @@ static int hdmi_pll_init(struct hdmi_ip_data *ip_data)
r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
- r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */
+ r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */
hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);
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