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authorTomi Valkeinen <tomi.valkeinen@ti.com>2014-09-29 20:46:15 +0000
committerTomi Valkeinen <tomi.valkeinen@ti.com>2014-10-22 11:33:10 +0300
commit26450d452bef641d4863fcc9f905779844fc3353 (patch)
tree8f9fe0b56b18cd5e2acb9cb1cfecaaeb4082ccdb /drivers/video
parent0856eba75cc65080997601aa6e5d02b46c8314d9 (diff)
downloadop-kernel-dev-26450d452bef641d4863fcc9f905779844fc3353.zip
op-kernel-dev-26450d452bef641d4863fcc9f905779844fc3353.tar.gz
OMAPDSS: DISPC: fix mflag offset
The register offset for DISPC_OVL_MFLAG_THRESHOLD is wrong, fix it. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/fbdev/omap2/dss/dispc.h3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/video/fbdev/omap2/dss/dispc.h b/drivers/video/fbdev/omap2/dss/dispc.h
index 78edb44..3043d6e 100644
--- a/drivers/video/fbdev/omap2/dss/dispc.h
+++ b/drivers/video/fbdev/omap2/dss/dispc.h
@@ -101,8 +101,7 @@
DISPC_FIR_COEF_V2_OFFSET(n, i))
#define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \
DISPC_PRELOAD_OFFSET(n))
-#define DISPC_OVL_MFLAG_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
- DISPC_MFLAG_THRESHOLD_OFFSET(n))
+#define DISPC_OVL_MFLAG_THRESHOLD(n) DISPC_MFLAG_THRESHOLD_OFFSET(n)
/* DISPC up/downsampling FIR filter coefficient structure */
struct dispc_coef {
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