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| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2013-11-14 13:46:32 +0200 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2013-12-30 16:14:15 +0200 |
| commit | ac9f24211e4cf9cc30122a7e0d830eba2cace14b (patch) | |
| tree | 75d5c716649bee9f787bba933ab820ea90080238 /drivers/video/omap2/dss/hdmi_wp.c | |
| parent | 8ee5c8427110e53e4eb71a872092e97973d9b940 (diff) | |
| download | op-kernel-dev-ac9f24211e4cf9cc30122a7e0d830eba2cace14b.zip op-kernel-dev-ac9f24211e4cf9cc30122a7e0d830eba2cace14b.tar.gz | |
OMAPDSS: fix debug prints
Fix debug prints all over omapdss:
* add missing linefeeds
* change pr_err/pr_debug to DSSERR/DSSDBG
* add missing DSS_SUBSYS_NAMEs
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/hdmi_wp.c')
| -rw-r--r-- | drivers/video/omap2/dss/hdmi_wp.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/video/omap2/dss/hdmi_wp.c b/drivers/video/omap2/dss/hdmi_wp.c index 8151d89..fa8e094 100644 --- a/drivers/video/omap2/dss/hdmi_wp.c +++ b/drivers/video/omap2/dss/hdmi_wp.c @@ -8,6 +8,8 @@ * the Free Software Foundation. */ +#define DSS_SUBSYS_NAME "HDMIWP" + #include <linux/kernel.h> #include <linux/err.h> #include <linux/io.h> @@ -76,7 +78,7 @@ int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val) /* Status of the power control of HDMI PHY */ if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val) != val) { - pr_err("Failed to set PHY power mode to %d\n", val); + DSSERR("Failed to set PHY power mode to %d\n", val); return -ETIMEDOUT; } @@ -92,7 +94,7 @@ int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val) /* wait till PHY_PWR_STATUS is set */ if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val) != val) { - pr_err("Failed to set PLL_PWR_STATUS\n"); + DSSERR("Failed to set PLL_PWR_STATUS\n"); return -ETIMEDOUT; } @@ -129,7 +131,7 @@ void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, { u32 r; bool vsync_pol, hsync_pol; - pr_debug("Enter hdmi_wp_video_config_interface\n"); + DSSDBG("Enter hdmi_wp_video_config_interface\n"); vsync_pol = timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH; hsync_pol = timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH; @@ -148,7 +150,7 @@ void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, u32 timing_h = 0; u32 timing_v = 0; - pr_debug("Enter hdmi_wp_video_config_timing\n"); + DSSDBG("Enter hdmi_wp_video_config_timing\n"); timing_h |= FLD_VAL(timings->hbp, 31, 20); timing_h |= FLD_VAL(timings->hfp, 19, 8); @@ -164,7 +166,7 @@ void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, struct omap_video_timings *timings, struct hdmi_config *param) { - pr_debug("Enter hdmi_wp_video_init_format\n"); + DSSDBG("Enter hdmi_wp_video_init_format\n"); video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444; video_fmt->y_res = param->timings.y_res; |
