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authorTomi Valkeinen <tomi.valkeinen@ti.com>2012-08-22 16:00:31 +0300
committerTomi Valkeinen <tomi.valkeinen@ti.com>2012-09-24 16:50:09 +0300
commitf8ef3d696651df01029d289f1e15c02d4f566610 (patch)
treea3de4661dccff8af131e13ad7f41dd90036702ad /drivers/video/omap2/dss/dss_features.h
parentde09e4555592986219132b518c3f7834a28823cd (diff)
downloadop-kernel-dev-f8ef3d696651df01029d289f1e15c02d4f566610.zip
op-kernel-dev-f8ef3d696651df01029d289f1e15c02d4f566610.tar.gz
OMAPDSS: DSI: Add FEAT_DSI_PLL_SELFREQDCO
Add FEAT_DSI_PLL_SELFREQDCO. OMAP5's DSI PLL has a new configuration option that needs to be programmed depending on the PLL's output clock frequency. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/dss_features.h')
-rw-r--r--drivers/video/omap2/dss/dss_features.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
index b81d603..f9b9d28 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -65,6 +65,7 @@ enum dss_feat_id {
/* An unknown HW bug causing the normal FIFO thresholds not to work */
FEAT_OMAP3_DSI_FIFO_BUG,
FEAT_BURST_2D,
+ FEAT_DSI_PLL_SELFREQDCO,
};
/* DSS register field id */
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