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authorTomi Valkeinen <tomi.valkeinen@ti.com>2012-09-24 15:15:57 +0300
committerTomi Valkeinen <tomi.valkeinen@ti.com>2012-09-24 16:50:10 +0300
commit77ccbfbb07764841500addb570ad61b9868a964d (patch)
tree4804b50cc9e45739746311ea8cd2f8281ed37623 /drivers/video/omap2/dss/dss_features.h
parent2ac80fbea1018404560294797da86d5e72a807f4 (diff)
downloadop-kernel-dev-77ccbfbb07764841500addb570ad61b9868a964d.zip
op-kernel-dev-77ccbfbb07764841500addb570ad61b9868a964d.tar.gz
OMAPDSS: DSI: Add code to disable PHY DCC
OMAP5 DSI PHY has DCC (Duty Cycle Corrector) block, and by default DCC is enabled and thus the PLL clock is divided by 2 to get the DSI DDR clk. This divider has been 4 for all previous OMAPs, and changing it needs some reorganization of the code. The DCC can be disabled, and in that case the divider is back to the old 4. This patch adds dss feature for the DCC, and adds code to always disable the DCC. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/dss_features.h')
-rw-r--r--drivers/video/omap2/dss/dss_features.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
index 0020bf6..aacad86 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -67,6 +67,7 @@ enum dss_feat_id {
FEAT_BURST_2D,
FEAT_DSI_PLL_SELFREQDCO,
FEAT_DSI_PLL_REFSEL,
+ FEAT_DSI_PHY_DCC,
};
/* DSS register field id */
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