OMAPDSS: cleanup fck parent handling

The dss parent_clk_name currently points to a clock node which we use to
change the fclk rate. Now that we have CLK_SET_RATE_PARENT properly set,
we can set the rate directly to the fclk node.

However, we still need to calculate the possible clock rates. For this,
we need the rate of the parent of the current parent_clk.

To simplify the code, this patch changes the parent_clk_name to point to
the above mentioned parent, so that we can get the rate directly.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

1 files changed, 0 insertions, 1 deletions

diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index ead1960..6fc786f 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -242,7 +242,6 @@ enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
 void dss_set_venc_output(enum omap_dss_venc_type type);
 void dss_set_dac_pwrdn_bgz(bool enable);
 
-unsigned long dss_get_dpll4_rate(void);
 int dss_set_fck_rate(unsigned long rate);
 
 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);