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author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2013-03-05 16:34:05 +0200 |
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committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2013-04-03 15:19:17 +0300 |
commit | 43417823fd8210edb7e714bea82ea9bd77089635 (patch) | |
tree | ff0679cce0ad56cab87a047897aab236371e1f49 /drivers/video/omap2/dss/dss.c | |
parent | 7c284e6ee3710e96bf246e6b52032f3d766fa094 (diff) | |
download | op-kernel-dev-43417823fd8210edb7e714bea82ea9bd77089635.zip op-kernel-dev-43417823fd8210edb7e714bea82ea9bd77089635.tar.gz |
OMAPDSS: DSS: add new clock calculation code
Add new way to iterate over DSS clock divisors. dss_div_calc() provides
a generic way to go over all the divisors, within given clock range.
dss_div_calc() will call a callback function for each divider set,
making the function reusable for all use cases.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/dss.c')
-rw-r--r-- | drivers/video/omap2/dss/dss.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 054c2a2..eba4127 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -473,6 +473,45 @@ int dss_calc_clock_rates(struct dss_clock_info *cinfo) return 0; } +bool dss_div_calc(unsigned long fck_min, dss_div_calc_func func, void *data) +{ + int fckd, fckd_start, fckd_stop; + unsigned long fck; + unsigned long fck_hw_max; + unsigned long fckd_hw_max; + unsigned long prate; + + if (dss.dpll4_m4_ck == NULL) { + /* + * TODO: dss1_fclk can be changed on OMAP2, but the available + * dividers are not continuous. We just use the pre-set rate for + * now. + */ + fck = clk_get_rate(dss.dss_clk); + fckd = 1; + return func(fckd, fck, data); + } + + fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); + fckd_hw_max = dss.feat->fck_div_max; + + prate = dss_get_dpll4_rate() * dss.feat->dss_fck_multiplier; + + fck_min = fck_min ? fck_min : 1; + + fckd_start = min(prate / fck_min, fckd_hw_max); + fckd_stop = max(DIV_ROUND_UP(prate, fck_hw_max), 1ul); + + for (fckd = fckd_start; fckd >= fckd_stop; --fckd) { + fck = prate / fckd; + + if (func(fckd, fck, data)) + return true; + } + + return false; +} + int dss_set_clock_div(struct dss_clock_info *cinfo) { if (dss.dpll4_m4_ck) { |