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| author | Chandrabhanu Mahapatra <cmahapatra@ti.com> | 2012-06-29 10:43:13 +0530 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2012-06-29 09:41:24 +0300 |
| commit | e86d456a23f3ecbb97704e63899ecfd6ec54b8d8 (patch) | |
| tree | 6984403531a2af514031916a20ff6d37c15c4f22 /drivers/video/omap2/dss/dispc.h | |
| parent | ff6331e25e3e02de17deef9a1e96334dad29e097 (diff) | |
| download | op-kernel-dev-e86d456a23f3ecbb97704e63899ecfd6ec54b8d8.zip op-kernel-dev-e86d456a23f3ecbb97704e63899ecfd6ec54b8d8.tar.gz | |
OMAPDSS: Add LCD3 overlay manager and Clock and IRQ support
The support for LCD3 manager has been added into the manager module. LCD3 panel
has registers as DISPC_CONTROL3 and DISPC_CONFIG3 just like those in LCD and
LCD2 panels. These registers control the Display Controller (DISPC) module for
LCD3 output. The three LCDs support Display Serial Interface (DSI), Remote Frame
Buffer Interface (RFBI) and Parallel CMOS Output Interface (DPI). These LCDs can
be connected through parallel output interface using DISPC and RFBI or DPI. For
serial interface DSS uses DSI.
The LCD3 panel, just like LCD and LCD2 panels, has a clock switch in DSS_CTRL
register which has been enabled. The clock switch chooses between DSS_CLK and
DPLL_DSI1_C_CLK1 as source for LCD3_CLK. New IRQs as DISPC_IRQ_VSYNC3,
DISPC_IRQ_FRAMEDONE3, DISPC_IRQ_ACBIAS_COUNT_STAT3 and DISPC_IRQ_SYNC_LOST3 have
been added specific to the new manager.
Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/dispc.h')
| -rw-r--r-- | drivers/video/omap2/dss/dispc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/video/omap2/dss/dispc.h b/drivers/video/omap2/dss/dispc.h index 420c980..92d8a9b 100644 --- a/drivers/video/omap2/dss/dispc.h +++ b/drivers/video/omap2/dss/dispc.h @@ -36,6 +36,8 @@ #define DISPC_CONTROL2 0x0238 #define DISPC_CONFIG2 0x0620 #define DISPC_DIVISOR 0x0804 +#define DISPC_CONTROL3 0x0848 +#define DISPC_CONFIG3 0x084C /* DISPC overlay registers */ #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \ |
