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| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2013-04-10 14:12:14 +0300 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2014-03-05 08:33:30 +0200 |
| commit | d8d789416aa71253c6532c9adc7469cb947031f6 (patch) | |
| tree | f918421f7f59ccbe8753572b270d241d9cfccede /drivers/video/omap2/dss/dispc.c | |
| parent | eba358435b21520a93180ec3021754c0e387b1f7 (diff) | |
| download | op-kernel-dev-d8d789416aa71253c6532c9adc7469cb947031f6.zip op-kernel-dev-d8d789416aa71253c6532c9adc7469cb947031f6.tar.gz | |
OMAPDSS: convert pixel clock to common videomode style
omapdss has its own video-timings struct, but we want to move the common
videomode.
The first step is to change the omapdss's pixelclock unit from kHz to
Hz. Also, omapdss uses "pixel_clock" field name, whereas the common
videomode uses "pixelclock" field name. This patch changes the field
name also, as that makes it easy to spot any non-converted pixel_clock
uses.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/dispc.c')
| -rw-r--r-- | drivers/video/omap2/dss/dispc.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 1659aa9..b801be4 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -2873,7 +2873,7 @@ bool dispc_mgr_timings_ok(enum omap_channel channel, timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res); - timings_ok &= _dispc_mgr_pclk_ok(channel, timings->pixel_clock * 1000); + timings_ok &= _dispc_mgr_pclk_ok(channel, timings->pixelclock); if (dss_mgr_is_lcd(channel)) { timings_ok &= _dispc_lcd_timings_ok(timings->hsw, timings->hfp, @@ -2968,10 +2968,10 @@ void dispc_mgr_set_timings(enum omap_channel channel, xtot = t.x_res + t.hfp + t.hsw + t.hbp; ytot = t.y_res + t.vfp + t.vsw + t.vbp; - ht = (timings->pixel_clock * 1000) / xtot; - vt = (timings->pixel_clock * 1000) / xtot / ytot; + ht = timings->pixelclock / xtot; + vt = timings->pixelclock / xtot / ytot; - DSSDBG("pck %u\n", timings->pixel_clock); + DSSDBG("pck %u\n", timings->pixelclock); DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp); DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n", |
