diff options
| author | Sean Paul <seanpaul@chromium.org> | 2012-10-31 23:21:00 +0000 |
|---|---|---|
| committer | Jingoo Han <jg1.han@samsung.com> | 2012-11-29 10:33:27 +0900 |
| commit | 49ce41f38b307d00cbcbc76721e0db2208915b44 (patch) | |
| tree | 9c8e36f221802fd50615081404f734be169de9b3 /drivers/video/exynos | |
| parent | fadec4b7e59e3a89c43dcba1c9812a9f99d2a61a (diff) | |
| download | op-kernel-dev-49ce41f38b307d00cbcbc76721e0db2208915b44.zip op-kernel-dev-49ce41f38b307d00cbcbc76721e0db2208915b44.tar.gz | |
video: exynos_dp: Get pll lock before pattern set
According to the exynos datasheet (Figure 49-10), we should wait for PLL
lock before programming the training pattern when doing software eDP
link training.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Diffstat (limited to 'drivers/video/exynos')
| -rw-r--r-- | drivers/video/exynos/exynos_dp_core.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/video/exynos/exynos_dp_core.c b/drivers/video/exynos/exynos_dp_core.c index 7161f9f..d60f8da 100644 --- a/drivers/video/exynos/exynos_dp_core.c +++ b/drivers/video/exynos/exynos_dp_core.c @@ -265,7 +265,7 @@ static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp, static int exynos_dp_link_start(struct exynos_dp_device *dp) { u8 buf[4]; - int lane, lane_count, retval; + int lane, lane_count, pll_tries, retval; lane_count = dp->link_train.lane_count; @@ -298,6 +298,18 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp) exynos_dp_set_lane_lane_pre_emphasis(dp, PRE_EMPHASIS_LEVEL_0, lane); + /* Wait for PLL lock */ + pll_tries = 0; + while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + if (pll_tries == DP_TIMEOUT_LOOP_COUNT) { + dev_err(dp->dev, "Wait for PLL lock timed out\n"); + return -ETIMEDOUT; + } + + pll_tries++; + usleep_range(90, 120); + } + /* Set training pattern 1 */ exynos_dp_set_training_pattern(dp, TRAINING_PTN1); |
