diff options
| author | Neil Zhang <zhangwm@marvell.com> | 2011-10-12 16:49:36 +0800 |
|---|---|---|
| committer | Felipe Balbi <balbi@ti.com> | 2011-10-13 20:42:06 +0300 |
| commit | daec765da767e4a6a30e1298862b28f2cae9a73f (patch) | |
| tree | af15335fc0121b7e9b36519c6dafa5976ea587d8 /drivers/usb | |
| parent | 046b07ac0458fba8c5ca8d9ee04658c02066ee03 (diff) | |
| download | op-kernel-dev-daec765da767e4a6a30e1298862b28f2cae9a73f.zip op-kernel-dev-daec765da767e4a6a30e1298862b28f2cae9a73f.tar.gz | |
usb: gadget: mv_udc: fix dtd dma confusion
The controller will prime failure sometimes when do the iperf test.
Add delay to wait controller release dtd dma before we free it.
Then the issue is gone.
Signed-off-by: Neil Zhang <zhangwm@marvell.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb')
| -rw-r--r-- | drivers/usb/gadget/mv_udc_core.c | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/drivers/usb/gadget/mv_udc_core.c b/drivers/usb/gadget/mv_udc_core.c index ffa6f30..9d960f1 100644 --- a/drivers/usb/gadget/mv_udc_core.c +++ b/drivers/usb/gadget/mv_udc_core.c @@ -138,6 +138,7 @@ static int process_ep_req(struct mv_udc *udc, int index, int i, direction; int retval = 0; u32 errors; + u32 bit_pos; curr_dqh = &udc->ep_dqh[index]; direction = index % 2; @@ -155,10 +156,20 @@ static int process_ep_req(struct mv_udc *udc, int index, errors = curr_dtd->size_ioc_sts & DTD_ERROR_MASK; if (!errors) { - remaining_length += + remaining_length = (curr_dtd->size_ioc_sts & DTD_PACKET_SIZE) >> DTD_LENGTH_BIT_POS; actual -= remaining_length; + + if (remaining_length) { + if (direction) { + dev_dbg(&udc->dev->dev, + "TX dTD remains data\n"); + retval = -EPROTO; + break; + } else + break; + } } else { dev_info(&udc->dev->dev, "complete_tr error: ep=%d %s: error = 0x%x\n", @@ -180,6 +191,20 @@ static int process_ep_req(struct mv_udc *udc, int index, if (retval) return retval; + if (direction == EP_DIR_OUT) + bit_pos = 1 << curr_req->ep->ep_num; + else + bit_pos = 1 << (16 + curr_req->ep->ep_num); + + while ((curr_dqh->curr_dtd_ptr == curr_dtd->td_dma)) { + if (curr_dtd->dtd_next == EP_QUEUE_HEAD_NEXT_TERMINATE) { + while (readl(&udc->op_regs->epstatus) & bit_pos) + udelay(1); + break; + } + udelay(1); + } + curr_req->req.actual = actual; return 0; |
