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authorNikita Yushchenko <nyushchenko@dev.rtsoft.ru>2014-04-28 19:23:44 +0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-05-03 18:04:28 -0400
commitd183c81929beeba842b74422f754446ef2b8b49c (patch)
treeeb9a39ac4b557f66ddbfd2007c246b02f3ee7e7d /drivers/usb
parentdf602c2d2358f02c6e49cffc5b49b9daa16db033 (diff)
downloadop-kernel-dev-d183c81929beeba842b74422f754446ef2b8b49c.zip
op-kernel-dev-d183c81929beeba842b74422f754446ef2b8b49c.tar.gz
fsl-usb: do not test for PHY_CLK_VALID bit on controller version 1.6
Per reference manuals of Freescale P1020 and P2020 SoCs, USB controller present in these SoCs has bit 17 of USBx_CONTROL register marked as Reserved - there is no PHY_CLK_VALID bit there. Testing for this bit in ehci_fsl_setup_phy() behaves differently on two P1020RDB boards available here - on one board test passes and fsl-usb init succeeds, but on other board test fails, causing fsl-usb init to fail. This patch changes ehci_fsl_setup_phy() not to test PHY_CLK_VALID on controller version 1.6 that (per manual) does not have this bit. Signed-off-by: Nikita Yushchenko <nyushchenko@dev.rtsoft.ru> Cc: stable <stable@vger.kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/usb')
-rw-r--r--drivers/usb/host/ehci-fsl.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 6f2c8d3..cf2734b 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -248,7 +248,8 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
break;
}
- if (pdata->have_sysif_regs && pdata->controller_ver &&
+ if (pdata->have_sysif_regs &&
+ pdata->controller_ver > FSL_USB_VER_1_6 &&
(phy_mode == FSL_USB2_PHY_ULPI)) {
/* check PHY_CLK_VALID to get phy clk valid */
if (!(spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &
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