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| author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2011-06-06 14:19:03 +0900 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-06-07 09:10:10 -0700 |
| commit | e73a9891b3a1c9fc0970e0c9dbe2cc47933ad752 (patch) | |
| tree | a40457485733fc6a08eae7f0d5efcbc98cf93a7d /drivers/usb/renesas_usbhs/common.h | |
| parent | 0cb7e61d16ac68a2c5dd73a00e211287848d16e7 (diff) | |
| download | op-kernel-dev-e73a9891b3a1c9fc0970e0c9dbe2cc47933ad752.zip op-kernel-dev-e73a9891b3a1c9fc0970e0c9dbe2cc47933ad752.tar.gz | |
usb: renesas_usbhs: add DMAEngine support
USB DMA was installed on "normal DMAC" when SH7724 or older SuperH,
but the "USB-DMAC" was prepared on recent SuperH.
These 2 DMAC have a little bit different behavior.
This patch add DMAEngine code for "normal DMAC",
but it is still using PIO fifo.
The DMA fifo will be formally supported in the future.
You can enable DMA fifo by local fixup
usbhs_fifo_pio_push_handler -> usbhs_fifo_dma_push_handler
usbhs_fifo_pio_pop_handler -> usbhs_fifo_dma_pop_handler
on usbhsg_ep_enable.
This DMAEngine was tested by g_file_storage on SH7724 Ecovec board
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/renesas_usbhs/common.h')
| -rw-r--r-- | drivers/usb/renesas_usbhs/common.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/drivers/usb/renesas_usbhs/common.h b/drivers/usb/renesas_usbhs/common.h index 06d7239..b410463 100644 --- a/drivers/usb/renesas_usbhs/common.h +++ b/drivers/usb/renesas_usbhs/common.h @@ -36,6 +36,12 @@ struct usbhs_priv; #define CFIFO 0x0014 #define CFIFOSEL 0x0020 #define CFIFOCTR 0x0022 +#define D0FIFO 0x0100 +#define D0FIFOSEL 0x0028 +#define D0FIFOCTR 0x002A +#define D1FIFO 0x0120 +#define D1FIFOSEL 0x002C +#define D1FIFOCTR 0x002E #define INTENB0 0x0030 #define INTENB1 0x0032 #define BRDYENB 0x0036 @@ -60,6 +66,30 @@ struct usbhs_priv; #define PIPEMAXP 0x006C #define PIPEPERI 0x006E #define PIPEnCTR 0x0070 +#define PIPE1TRE 0x0090 +#define PIPE1TRN 0x0092 +#define PIPE2TRE 0x0094 +#define PIPE2TRN 0x0096 +#define PIPE3TRE 0x0098 +#define PIPE3TRN 0x009A +#define PIPE4TRE 0x009C +#define PIPE4TRN 0x009E +#define PIPE5TRE 0x00A0 +#define PIPE5TRN 0x00A2 +#define PIPEBTRE 0x00A4 +#define PIPEBTRN 0x00A6 +#define PIPECTRE 0x00A8 +#define PIPECTRN 0x00AA +#define PIPEDTRE 0x00AC +#define PIPEDTRN 0x00AE +#define PIPEETRE 0x00B0 +#define PIPEETRN 0x00B2 +#define PIPEFTRE 0x00B4 +#define PIPEFTRN 0x00B6 +#define PIPE9TRE 0x00B8 +#define PIPE9TRN 0x00BA +#define PIPEATRE 0x00BC +#define PIPEATRN 0x00BE /* SYSCFG */ #define SCKE (1 << 10) /* USB Module Clock Enable */ @@ -78,6 +108,7 @@ struct usbhs_priv; #define RHST_HIGH_SPEED 3 /* High-speed connection */ /* CFIFOSEL */ +#define DREQE (1 << 12) /* DMA Transfer Request Enable */ #define MBW_32 (0x2 << 10) /* CFIFO Port Access Bit Width */ /* CFIFOCTR */ @@ -164,6 +195,10 @@ struct usbhs_priv; #define CCPL (1 << 2) /* Control Transfer End Enable */ +/* PIPEnTRE */ +#define TRENB (1 << 9) /* Transaction Counter Enable */ +#define TRCLR (1 << 8) /* Transaction Counter Clear */ + /* FRMNUM */ #define FRNM_MASK (0x7FF) |
