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| author | Stefan Agner <stefan@agner.ch> | 2016-07-19 13:13:05 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-08-31 15:48:28 +0200 |
| commit | d68827c62a105eec547945daedf4d1d3e283717d (patch) | |
| tree | ca79c531d0d11f14ab1c04e0816dd562a2169ece /drivers/tty/serial/fsl_lpuart.c | |
| parent | d6b0d2f243fef6cb87f5338bf06c2330175f106f (diff) | |
| download | op-kernel-dev-d68827c62a105eec547945daedf4d1d3e283717d.zip op-kernel-dev-d68827c62a105eec547945daedf4d1d3e283717d.tar.gz | |
tty: serial: fsl_lpuart: fix clearing of receive flag
Commit 8e4934c6d6c6 ("tty: serial: fsl_lpuart: clear receive flag on FIFO
flush") implemented clearing of the receive flag by reading the status register
only. It turned out that even though we flush the FIFO afterwards, a explicit
read of the data register is still required.
This leads to a FIFO underrun. To avoid this, follow the advice in the overrun
"Operation section": Unconditionally clear RXUF after using RXFLUSH.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty/serial/fsl_lpuart.c')
| -rw-r--r-- | drivers/tty/serial/fsl_lpuart.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index e46cffd..7164632 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -935,13 +935,16 @@ static void lpuart_setup_watermark(struct lpuart_port *sport) writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, sport->port.membase + UARTPFIFO); - /* explicitly clear RDRF */ - readb(sport->port.membase + UARTSR1); - /* flush Tx and Rx FIFO */ writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); + /* explicitly clear RDRF */ + if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { + readb(sport->port.membase + UARTDR); + writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); + } + writeb(0, sport->port.membase + UARTTWFIFO); writeb(1, sport->port.membase + UARTRWFIFO); |
