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authorMike Rapoport <mike.rapoport@gmail.com>2016-02-10 18:33:57 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-02-11 19:52:37 -0800
commit5557eb17b3f14b92f2512d43ff6d68c6f0a609ef (patch)
tree9f3466352790d3f915557c6dc0e5cbd868907097 /drivers/staging/sm750fb
parent79254c60db6a5cbb72a9cb5eb1c3c50d6cdf755a (diff)
downloadop-kernel-dev-5557eb17b3f14b92f2512d43ff6d68c6f0a609ef.zip
op-kernel-dev-5557eb17b3f14b92f2512d43ff6d68c6f0a609ef.tar.gz
staging: sm750fb: use BIT macro for PLL_CTRL single-bit fields
Replace complex defintion of PLL_CTRL fields with BIT() macro and use open-coded implementation for PLL register manipulations. Signed-off-by: Mike Rapoport <mike.rapoport@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/sm750fb')
-rw-r--r--drivers/staging/sm750fb/ddk750_chip.c5
-rw-r--r--drivers/staging/sm750fb/ddk750_display.c6
-rw-r--r--drivers/staging/sm750fb/ddk750_reg.h12
3 files changed, 6 insertions, 17 deletions
diff --git a/drivers/staging/sm750fb/ddk750_chip.c b/drivers/staging/sm750fb/ddk750_chip.c
index 277e5c5..467b858 100644
--- a/drivers/staging/sm750fb/ddk750_chip.c
+++ b/drivers/staging/sm750fb/ddk750_chip.c
@@ -363,10 +363,7 @@ unsigned int formatPllReg(pll_value_t *pPLL)
* register. On returning a 32 bit number, the value can be
* applied to any PLL in the calling function.
*/
- reg =
- FIELD_SET(0, PLL_CTRL, BYPASS, OFF)
- | FIELD_SET(0, PLL_CTRL, POWER, ON)
- | FIELD_SET(0, PLL_CTRL, INPUT, OSC)
+ reg = PLL_CTRL_POWER
#ifndef VALIDATION_CHIP
| FIELD_VALUE(0, PLL_CTRL, POD, pPLL->POD)
#endif
diff --git a/drivers/staging/sm750fb/ddk750_display.c b/drivers/staging/sm750fb/ddk750_display.c
index 5d1f9a5..a82253c 100644
--- a/drivers/staging/sm750fb/ddk750_display.c
+++ b/drivers/staging/sm750fb/ddk750_display.c
@@ -126,8 +126,7 @@ static void waitNextVerticalSync(int ctrl, int delay)
/* Do not wait when the Primary PLL is off or display control is already off.
This will prevent the software to wait forever. */
- if ((FIELD_GET(PEEK32(PANEL_PLL_CTRL), PLL_CTRL, POWER) ==
- PLL_CTRL_POWER_OFF) ||
+ if (!(PEEK32(PANEL_PLL_CTRL) & PLL_CTRL_POWER) ||
(FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, TIMING) ==
PANEL_DISPLAY_CTRL_TIMING_DISABLE)) {
return;
@@ -149,8 +148,7 @@ static void waitNextVerticalSync(int ctrl, int delay)
/* Do not wait when the Primary PLL is off or display control is already off.
This will prevent the software to wait forever. */
- if ((FIELD_GET(PEEK32(CRT_PLL_CTRL), PLL_CTRL, POWER) ==
- PLL_CTRL_POWER_OFF) ||
+ if (!(PEEK32(CRT_PLL_CTRL) & PLL_CTRL_POWER) ||
(FIELD_GET(PEEK32(CRT_DISPLAY_CTRL), CRT_DISPLAY_CTRL, TIMING) ==
CRT_DISPLAY_CTRL_TIMING_DISABLE)) {
return;
diff --git a/drivers/staging/sm750fb/ddk750_reg.h b/drivers/staging/sm750fb/ddk750_reg.h
index 1ad8d55..d13af39 100644
--- a/drivers/staging/sm750fb/ddk750_reg.h
+++ b/drivers/staging/sm750fb/ddk750_reg.h
@@ -517,15 +517,9 @@
#define PLL_CLK_COUNT_COUNTER 15:0
#define PANEL_PLL_CTRL 0x00005C
-#define PLL_CTRL_BYPASS 18:18
-#define PLL_CTRL_BYPASS_OFF 0
-#define PLL_CTRL_BYPASS_ON 1
-#define PLL_CTRL_POWER 17:17
-#define PLL_CTRL_POWER_OFF 0
-#define PLL_CTRL_POWER_ON 1
-#define PLL_CTRL_INPUT 16:16
-#define PLL_CTRL_INPUT_OSC 0
-#define PLL_CTRL_INPUT_TESTCLK 1
+#define PLL_CTRL_BYPASS BIT(18)
+#define PLL_CTRL_POWER BIT(17)
+#define PLL_CTRL_INPUT BIT(16)
#ifdef VALIDATION_CHIP
#define PLL_CTRL_OD 15:14
#else
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