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| author | Greg Kroah-Hartman <gregkh@suse.de> | 2010-10-28 09:44:56 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-10-28 09:44:56 -0700 |
| commit | e4c5bf8e3dca827a1b3a6fac494eae8c74b7e1e7 (patch) | |
| tree | ea51b391f7d74ca695dcb9f5e46eb02688a92ed9 /drivers/staging/rtl8712/rtl8712_gp_bitdef.h | |
| parent | 81280572ca6f54009edfa4deee563e8678784218 (diff) | |
| parent | a4ac0d847af9dd34d5953a5e264400326144b6b2 (diff) | |
| download | op-kernel-dev-e4c5bf8e3dca827a1b3a6fac494eae8c74b7e1e7.zip op-kernel-dev-e4c5bf8e3dca827a1b3a6fac494eae8c74b7e1e7.tar.gz | |
Merge 'staging-next' to Linus's tree
This merges the staging-next tree to Linus's tree and resolves
some conflicts that were present due to changes in other trees that were
affected by files here.
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/rtl8712/rtl8712_gp_bitdef.h')
| -rw-r--r-- | drivers/staging/rtl8712/rtl8712_gp_bitdef.h | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/drivers/staging/rtl8712/rtl8712_gp_bitdef.h b/drivers/staging/rtl8712/rtl8712_gp_bitdef.h new file mode 100644 index 0000000..35ca809 --- /dev/null +++ b/drivers/staging/rtl8712/rtl8712_gp_bitdef.h @@ -0,0 +1,54 @@ +#ifndef __RTL8712_GP_BITDEF_H__ +#define __RTL8712_GP_BITDEF_H__ + +/*GPIO_CTRL*/ +#define _GPIO_MOD_MSK 0xFF000000 +#define _GPIO_MOD_SHT 24 +#define _GPIO_IO_SEL_MSK 0x00FF0000 +#define _GPIO_IO_SEL_SHT 16 +#define _GPIO_OUT_MSK 0x0000FF00 +#define _GPIO_OUT_SHT 8 +#define _GPIO_IN_MSK 0x000000FF +#define _GPIO_IN_SHT 0 + +/*SYS_PINMUX_CFG*/ +#define _GPIOSEL_MSK 0x0003 +#define _GPIOSEL_SHT 0 + +/*LED_CFG*/ +#define _LED1SV BIT(7) +#define _LED1CM_MSK 0x0070 +#define _LED1CM_SHT 4 +#define _LED0SV BIT(3) +#define _LED0CM_MSK 0x0007 +#define _LED0CM_SHT 0 + +/*PHY_REG*/ +#define _HST_RDRDY_SHT 0 +#define _HST_RDRDY_MSK 0xFF +#define _HST_RDRDY BIT(_HST_RDRDY_SHT) +#define _CPU_WTBUSY_SHT 1 +#define _CPU_WTBUSY_MSK 0xFF +#define _CPU_WTBUSY BIT(_CPU_WTBUSY_SHT) + +/* 11. General Purpose Registers (Offset: 0x02E0 - 0x02FF)*/ + +/* 8192S GPIO Config Setting (offset 0x2F1, 1 byte)*/ + +/*----------------------------------------------------------------------------*/ + +#define GPIOMUX_EN BIT(3) /* When this bit is set to "1", + * GPIO PINs will switch to MAC + * GPIO Function*/ +#define GPIOSEL_GPIO 0 /* UART or JTAG or pure GPIO*/ +#define GPIOSEL_PHYDBG 1 /* PHYDBG*/ +#define GPIOSEL_BT 2 /* BT_coex*/ +#define GPIOSEL_WLANDBG 3 /* WLANDBG*/ +#define GPIOSEL_GPIO_MASK (~(BIT(0)|BIT(1))) +/* HW Readio OFF switch (GPIO BIT) */ +#define HAL_8192S_HW_GPIO_OFF_BIT BIT(3) +#define HAL_8192S_HW_GPIO_OFF_MASK 0xF7 +#define HAL_8192S_HW_GPIO_WPS_BIT BIT(4) + +#endif /*__RTL8712_GP_BITDEF_H__*/ + |
