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| author | Xenia Ragiadakou <burzalodowa@gmail.com> | 2013-06-23 06:15:18 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-06-24 16:08:33 -0700 |
| commit | 26f3561db708efa91e005b8837fb3e49c17b424f (patch) | |
| tree | 4f7eeed079bb421b91c0c52450668d0641a306e6 /drivers/staging/rtl8192u | |
| parent | a60d4d6896fff32da512b233e0726a6423ff1562 (diff) | |
| download | op-kernel-dev-26f3561db708efa91e005b8837fb3e49c17b424f.zip op-kernel-dev-26f3561db708efa91e005b8837fb3e49c17b424f.tar.gz | |
staging: rtl8192u: replace msleep(1) with usleep_range() in r819xU_phy.c
This patch fixes the following checkpatch warning:
WARNING: msleep < 20ms can sleep for up to 20ms
The implementation of msleep() is based on jiffies timeout
subsystem. Hence, its resolution is constrained by the value
of HZ tick rate. When HZ variable is configured to 100,
the jiffies variable is updated every 10 ms, so a timeout
of 1ms cannot be met using jiffies (it will be rounded up
to 10ms).
This patch replaces msleep(1) with usleep_range(1000, 1000).
usleep_range() uses hrtimers subsystem which is not bound
to HZ value and can provide microsecond-level resolution.
Signed-off-by: Xenia Ragiadakou <burzalodowa@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/rtl8192u')
| -rw-r--r-- | drivers/staging/rtl8192u/r819xU_phy.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/staging/rtl8192u/r819xU_phy.c b/drivers/staging/rtl8192u/r819xU_phy.c index edb5df2..92f0f90 100644 --- a/drivers/staging/rtl8192u/r819xU_phy.c +++ b/drivers/staging/rtl8192u/r819xU_phy.c @@ -185,7 +185,7 @@ u32 rtl8192_phy_RFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, /* TODO: we should not delay such a long time. Ask for help from SD3 */ - msleep(1); + usleep_range(1000, 1000); ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); @@ -741,11 +741,11 @@ u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock, bMask12Bits, WriteData[i]); /* TODO: we should not delay for such a long time. Ask SD3 */ - msleep(1); + usleep_range(1000, 1000); reg = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits); - msleep(1); + usleep_range(1000, 1000); break; default: |
