staging: rtl8192su: various updates

Signed-off-by: Florian Schilhabel <florian.c.schilhabel@googlemail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

1 files changed, 87 insertions, 96 deletions

diff --git a/drivers/staging/rtl8192su/r8192S_phy.c b/drivers/staging/rtl8192su/r8192S_phy.c
index fb7d676..a5fc2d1 100644
--- a/drivers/staging/rtl8192su/r8192S_phy.c
+++ b/drivers/staging/rtl8192su/r8192S_phy.c
@@ -3485,9 +3485,10 @@ void ChkFwCmdIoDone(struct net_device* dev)
 //
 void phy_SetFwCmdIOCallback(struct net_device* dev)
 {
-	u32 	 	input;
-	static u32 ScanRegister;
 	struct r8192_priv *priv = ieee80211_priv(dev);
+	PRT_HIGH_THROUGHPUT	pHTInfo = priv->ieee80211->pHTInfo;
+	rt_firmware		*pFirmware = priv->pFirmware;
+	u32	input, CurrentAID = 0;;
 	if(!priv->up)
 	{
 		RT_TRACE(COMP_CMD, "SetFwCmdIOTimerCallback(): driver is going to unload\n");
@@ -3496,61 +3497,22 @@ void phy_SetFwCmdIOCallback(struct net_device* dev)
 
 	RT_TRACE(COMP_CMD, "--->SetFwCmdIOTimerCallback(): Cmd(%#x), SetFwCmdInProgress(%d)\n", priv->CurrentFwCmdIO, priv->SetFwCmdInProgress);
 
-	switch(priv->CurrentFwCmdIO)
+	if(pFirmware->FirmwareVersion >= 0x34)
 	{
-		case FW_CMD_HIGH_PWR_ENABLE:
-			if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0)
-				write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE);
-			break;
-
-		case FW_CMD_HIGH_PWR_DISABLE:
-			write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE);
-			break;
-
-		case FW_CMD_DIG_RESUME:
-			write_nic_dword(dev, WFM5, FW_DIG_RESUME);
-			break;
-
-		case FW_CMD_DIG_HALT:
-			write_nic_dword(dev, WFM5, FW_DIG_HALT);
-			break;
-
-		//
-		// <Roger_Notes> The following FW CMD IO was combined into single operation
-		// (i.e., to prevent number of system workitem out of resource!!).
-		// 2008.12.04.
-		//
-		case FW_CMD_RESUME_DM_BY_SCAN:
-			RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR enable and DIG resume!!\n");
-			if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0)
-			{
-				write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE); //break;
-				ChkFwCmdIoDone(dev);
-			}
-			write_nic_dword(dev, WFM5, FW_DIG_RESUME);
-			break;
-
-		case FW_CMD_PAUSE_DM_BY_SCAN:
-			RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR disable and DIG halt!!\n");
-			write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE); //break;
-			ChkFwCmdIoDone(dev);
-			write_nic_dword(dev, WFM5, FW_DIG_HALT);
+		switch(priv->CurrentFwCmdIO)
+		{
+			case FW_CMD_RA_REFRESH_N:
+				priv->CurrentFwCmdIO = FW_CMD_RA_REFRESH_N_COMB;
 			break;
-
-		//
-		// <Roger_Notes> The following FW CMD IO should be checked
-		// (i.e., workitem schedule timing issue!!).
-		// 2008.12.04.
-		//
-		case FW_CMD_DIG_DISABLE:
-			RT_TRACE(COMP_CMD, "[FW CMD] Set DIG disable!!\n");
-			write_nic_dword(dev, WFM5, FW_DIG_DISABLE);
+			case FW_CMD_RA_REFRESH_BG:
+				priv->CurrentFwCmdIO = FW_CMD_RA_REFRESH_BG_COMB;
 			break;
-
-		case FW_CMD_DIG_ENABLE:
-			RT_TRACE(COMP_CMD, "[FW CMD] Set DIG enable!!\n");
-			write_nic_dword(dev, WFM5, FW_DIG_ENABLE);
+			default:
 			break;
+		}
+	}
+	switch(priv->CurrentFwCmdIO)
+	{
 
 		case FW_CMD_RA_RESET:
 			write_nic_dword(dev, WFM5, FW_RA_RESET);
@@ -3561,82 +3523,111 @@ void phy_SetFwCmdIOCallback(struct net_device* dev)
 			break;
 
 		case FW_CMD_RA_REFRESH_N:
-			RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! N\n");
-			if(priv->ieee80211->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
+			RT_TRACE(COMP_CMD, "[FW CMD] Set RA n refresh!!\n");
+			if(pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
 				input = FW_RA_REFRESH;
 			else
-				input = FW_RA_REFRESH | (priv->ieee80211->pHTInfo->IOTRaFunc << 8);
+				input = FW_RA_REFRESH | (pHTInfo->IOTRaFunc << 8);
 			write_nic_dword(dev, WFM5, input);
+			ChkFwCmdIoDone(dev);
+			write_nic_dword(dev, WFM5, FW_RA_ENABLE_RSSI_MASK);
+			ChkFwCmdIoDone(dev);
 			break;
 		case FW_CMD_RA_REFRESH_BG:
-			RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! B/G\n");
+			RT_TRACE(COMP_CMD, "[FW CMD] Set RA BG refresh!!\n");
 			write_nic_dword(dev, WFM5, FW_RA_REFRESH);
 			ChkFwCmdIoDone(dev);
-			write_nic_dword(dev, WFM5, FW_RA_ENABLE_BG);
+			write_nic_dword(dev, WFM5, FW_RA_DISABLE_RSSI_MASK);
+			ChkFwCmdIoDone(dev);
+			break;
+
+		case FW_CMD_RA_REFRESH_N_COMB:
+			RT_TRACE(COMP_CMD, "[FW CMD] Set RA n Combo refresh!!\n");
+			if(pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
+				input = FW_RA_IOT_N_COMB;
+			else
+				input = FW_RA_IOT_N_COMB | (((pHTInfo->IOTRaFunc)&0x0f) << 8);
+			input = input |((pHTInfo->IOTPeer & 0xf) <<12);
+			RT_TRACE(COMP_CMD, "[FW CMD] Set RA/IOT Comb in n mode!! input(%#x)\n", input);
+			write_nic_dword(dev, WFM5, input);
+			ChkFwCmdIoDone(dev);
+			break;
+
+		case FW_CMD_RA_REFRESH_BG_COMB:
+			RT_TRACE(COMP_CMD, "[FW CMD] Set RA B/G Combo refresh!!\n");
+			if(pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
+				input = FW_RA_IOT_BG_COMB;
+			else
+				input = FW_RA_IOT_BG_COMB | (((pHTInfo->IOTRaFunc)&0x0f) << 8);
+			input = input |((pHTInfo->IOTPeer & 0xf) <<12);
+			RT_TRACE(COMP_CMD, "[FW CMD] Set RA/IOT Comb in B/G mode!! input(%#x)\n", input);
+			write_nic_dword(dev, WFM5, input);
+			ChkFwCmdIoDone(dev);
 			break;
 
 		case FW_CMD_IQK_ENABLE:
 			write_nic_dword(dev, WFM5, FW_IQK_ENABLE);
+			ChkFwCmdIoDone(dev);
 			break;
 
 		case FW_CMD_TXPWR_TRACK_ENABLE:
 			write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_ENABLE);
+			ChkFwCmdIoDone(dev);
 			break;
 
 		case FW_CMD_TXPWR_TRACK_DISABLE:
 			write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_DISABLE);
+			ChkFwCmdIoDone(dev);
 			break;
 
-		default:
-			RT_TRACE(COMP_CMD,"Unknown FW Cmd IO(%#x)\n", priv->CurrentFwCmdIO);
+		case FW_CMD_PAUSE_DM_BY_SCAN:
+			RT_TRACE(COMP_CMD,"[FW CMD] Pause DM by Scan!!\n");
+			rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
+			rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
+			rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);
 			break;
-	}
 
-	ChkFwCmdIoDone(dev);
-
-	switch(priv->CurrentFwCmdIO)
-	{
+		case FW_CMD_RESUME_DM_BY_SCAN:
+			RT_TRACE(COMP_CMD, "[FW CMD] Resume DM by Scan!!\n");
+			rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83);
+			PHY_SetTxPowerLevel8192S(dev, priv->chan);
+			break;
 		case FW_CMD_HIGH_PWR_DISABLE:
-			//if(pMgntInfo->bTurboScan)
-			{
-				//Lower initial gain
-				rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
-				rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
-				// CCA threshold
-				rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);
-				// Disable OFDM Part
-				rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x1);
-				ScanRegister = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector1,bMaskDWord);
-				rtl8192_setBBreg(dev, rOFDM0_RxDetector1, 0xf, 0xf);
-				rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
-			}
+			RT_TRACE(COMP_CMD, "[FW CMD] High Pwr Disable!!\n");
+			if(priv->DMFlag & HAL_DM_HIPWR_DISABLE)
+				break;
+			rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
+			rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
+			rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);
 			break;
 
 		case FW_CMD_HIGH_PWR_ENABLE:
-			//if(pMgntInfo->bTurboScan)
-			{
-				rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x36);
-				rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x36);
+			RT_TRACE(COMP_CMD, "[FW CMD] High Pwr Enable!!\n");
+			if(priv->DMFlag & HAL_DM_HIPWR_DISABLE)
+				break;
+			rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83);
+			break;
 
-				// CCA threshold
-				rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83);
-				// Enable OFDM Part
-				rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x0);
+		case FW_CMD_LPS_ENTER:
+			RT_TRACE(COMP_CMD, "[FW CMD] Enter LPS mode!!\n");
+			CurrentAID = priv->ieee80211->assoc_id;
+			write_nic_dword(dev, WFM5, (FW_LPS_ENTER| ((CurrentAID|0xc000)<<8))    );
+			ChkFwCmdIoDone(dev);
+			pHTInfo->IOTAction |=  HT_IOT_ACT_DISABLE_EDCA_TURBO;
+			break;
 
-				//LZM ADD because sometimes there is no FW_CMD_HIGH_PWR_DISABLE, this value will be 0.
-				if(ScanRegister != 0){
-				rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskDWord, ScanRegister);
-				}
+		case FW_CMD_LPS_LEAVE:
+			RT_TRACE(COMP_CMD, "[FW CMD] Leave LPS mode!!\n");
+			write_nic_dword(dev, WFM5, FW_LPS_LEAVE );
+			ChkFwCmdIoDone(dev);
+			pHTInfo->IOTAction &=  (~HT_IOT_ACT_DISABLE_EDCA_TURBO);
+			break;
 
-				if(priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R)
-					rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x3);
-				else
-					rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x1);
-			}
+		default:
 			break;
 	}
 
-	priv->SetFwCmdInProgress = false;// Clear FW CMD operation flag.
+	priv->SetFwCmdInProgress = false;
 	RT_TRACE(COMP_CMD, "<---SetFwCmdIOWorkItemCallback()\n");
 
 }