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authorSimon Guo <wei.guo.simon@gmail.com>2018-05-23 15:02:07 +0800
committerPaul Mackerras <paulus@ozlabs.org>2018-06-01 10:30:43 +1000
commit7284ca8a5eaee311d2e4aec73b2df9bd57e0cdcb (patch)
tree9425521c48ed9b4b5f073e0ba964262451f1da93 /drivers/staging/ipx
parent68ab07b985764ec5be816e7054a84b7ad121afc7 (diff)
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KVM: PPC: Book3S PR: Support TAR handling for PR KVM HTM
Currently guest kernel doesn't handle TAR facility unavailable and it always runs with TAR bit on. PR KVM will lazily enable TAR. TAR is not a frequent-use register and it is not included in SVCPU struct. Due to the above, the checkpointed TAR val might be a bogus TAR val. To solve this issue, we will make vcpu->arch.fscr tar bit consistent with shadow_fscr when TM is enabled. At the end of emulating treclaim., the correct TAR val need to be loaded into the register if FSCR_TAR bit is on. At the beginning of emulating trechkpt., TAR needs to be flushed so that the right tar val can be copied into tar_tm. Tested with: tools/testing/selftests/powerpc/tm/tm-tar tools/testing/selftests/powerpc/ptrace/ptrace-tm-tar (remove DSCR/PPR related testing). Signed-off-by: Simon Guo <wei.guo.simon@gmail.com> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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