diff options
| author | Alison Schofield <amsfield22@gmail.com> | 2016-03-21 15:39:53 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-03-28 07:30:36 -0700 |
| commit | a6634f83402c5c8baf636998143f956feecfa770 (patch) | |
| tree | 5699e7d1991f84ac456c4cbac9bcdd6a7014bf57 /drivers/staging/iio/adc | |
| parent | 017168b5fd913df50a80b65b9c086066f1484a13 (diff) | |
| download | op-kernel-dev-a6634f83402c5c8baf636998143f956feecfa770.zip op-kernel-dev-a6634f83402c5c8baf636998143f956feecfa770.tar.gz | |
staging: iio: use kernel preferred block commenting style
Use * on subsequent lines and trailing */ on a separate
line in block comments.
Signed-off-by: Alison Schofield <amsfield22@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/iio/adc')
| -rw-r--r-- | drivers/staging/iio/adc/ad7192.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/staging/iio/adc/ad7192.c b/drivers/staging/iio/adc/ad7192.c index f843f19..f91468e 100644 --- a/drivers/staging/iio/adc/ad7192.c +++ b/drivers/staging/iio/adc/ad7192.c @@ -35,10 +35,10 @@ #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */ #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */ #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */ -#define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit - * (AD7792)/24-bit (AD7192)) */ -#define AD7192_REG_FULLSALE 7 /* Full-Scale Register - * (RW, 16-bit (AD7792)/24-bit (AD7192)) */ +#define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */ + /* (AD7792)/24-bit (AD7192)) */ +#define AD7192_REG_FULLSALE 7 /* Full-Scale Register */ + /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */ /* Communications Register Bit Designations (AD7192_REG_COMM) */ #define AD7192_COMM_WEN BIT(7) /* Write Enable */ @@ -80,13 +80,13 @@ #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */ /* Mode Register: AD7192_MODE_CLKSRC options */ -#define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected - * from MCLK1 to MCLK2 */ +#define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/ + /* from MCLK1 to MCLK2 */ #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */ -#define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not - * available at the MCLK2 pin */ -#define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available - * at the MCLK2 pin */ +#define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */ + /* available at the MCLK2 pin */ +#define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/ + /* at the MCLK2 pin */ /* Configuration Register Bit Designations (AD7192_REG_CONF) */ |
